TPS54610
- 30-mΩ, 12-A Peak MOSFET Switches for High Efficiency at 6-A Continuous Output Source or Sink Current
- Adjustable Output Voltage Down to 0.9 V With 1.0% Accuracy
- Wide PWM Frequency: Fixed 350 kHz, 550 kHz or Adjustable 280 kHz to 700 kHz
- Synchronizable to 700 kHz
- Load Protected by Peak Current Limit and Thermal Shutdown
- Integrated Solution Reduces Board Area and Component Count
- SWIFT Documentation, Application Notes, and Design Software: www.ti.com/swift
The TPS54610 low-input voltage high-output current synchronous buck PWM converter integrates all required active components. Included on the substrate with the listed features are a true, high performance, voltage error amplifier that enables maximum performance and flexibility in choosing the output filter L and C components; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches 3 V; an internally or externally set slow-start circuit to limit inrush currents; and a power good output useful for processor/logic reset, fault signaling, and supply sequencing.
The TPS54610 is available in a thermally enhanced 28-pin HTSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. TI provides evaluation modules to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles.
기술 자료
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
TPS54610EVM-192 — 0.9V까지 출력을 조정할 수 있는 6A, 3~6VIN DC/DC 컨버터
The TPS54610EVM-192 kit allows the designer to easily evaluate the TPS54610 synchronous buck DC/DC converter with integrated 6 A continuous power MOSFETs. The input range is 3-6 V and the output voltage is adjustable down to 0.9 V (module preset to 3.3 V). Other voltages are possible by changing a (...)
TPS54610 Unencrypted PSpice Average Model Package (Rev. A)
TPS54610 Unencrypted PSpice Transient Model Package (Rev. A)
TIDA-00078 — I/Q 보정이 지원되는 다이렉트 다운 컨버전 시스템
The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HTSSOP (PWP) | 28 | Ultra Librarian |
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