SN74LVT543
- State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation
- Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
- Support Unregulated Battery Operation Down to 2.7 V
- Typical VOLP (Output Ground Bounce)< 0.8 V at VCC = 3.3 V, TA = 25°C
- ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors
- Support Live Insertion
- Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs
These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The 'LVT543 contain two sets of D-type latches for temporary
storage of data flowing in either direction. Separate latch-enable
(
or
) and output-enable(
or
) inputs are
provided for each register to permit independent control in either
direction of data flow.
The A-to-B enable (
)
input must be low in order to enter data from A or to output data
from B. If is low and
is low, the
A-to-B latches are transparent; a subsequent low-to-high transition
of puts the A
latches in the storage mode. With and both low, the
3-state B outputs are active and reflect the data present at the
output of the A latches. Data flow from B to A is similar but
requires using the 
,, and inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | 3.3-V ABT Octal Registered Transceivers With 3-State Outputs datasheet (Rev. D) | 1995. 7. 1 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈
14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (DW) | 24 | Ultra Librarian |