SN74LVCH32373A
- Member of the Texas Instruments Widebus+™ Family
- Operates from 1.65 V to 3.6 V
- Inputs accept voltages to 5.5 V
- Max tpd of 4.2 ns at 3.3 V
- Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
- Ioff supports partial-power-down mode operation
- Supports mixed-mode signal operation (5-V Input and output voltages with 3.3-V VCC)
- Bus hold on data inputs eliminates the need for external pullup/pulldown resistors
- Latch-up performance exceeds 250 mA per JESD 17
- ESD protection exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
기술 자료
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3개 모두 보기
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | SN74LVCH32373A datasheet (Rev. E) | 2020. 7. 21 | ||
| 애플리케이션 노트 | Power-Up Behavior of Clocked Devices (Rev. B) | PDF | HTML | 2022. 12. 15 | ||
| 애플리케이션 노트 | An Overview of Bus-Hold Circuit and the Applications (Rev. B) | 2018. 9. 17 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| NFBGA (NMJ) | 96 | Ultra Librarian |