SN74LVC2GU04

활성

2채널, 1.65V~5.5V 인버터

지금 주문하기

데이터 시트

document-pdfAcrobat Dual Inverter Gate--SN74LVC2GU04 datasheet (Rev. N) (영어)

SN74LVC2GU04

활성

지금 주문하기

제품 상세 정보

Technology family

LVC

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (µA)

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Unbuffered, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

IOL (max) (mA)

IOH (max) (mA)

-32

Supply current (max) (µA)

Input type

Standard CMOS

Output type

Push-Pull

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Unbuffered, Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

2.1875 mm² (— mm × — mm)

SOT-SC70 (DCK)

4.2 mm² (2 mm × 2.1 mm)

SOT-23 (DBV)

8.12 mm² (2.9 mm × 2.8 mm)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 3.7 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Unbuffered Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This dual inverter is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2GU04 device contains two inverters with unbuffered outputs and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This dual inverter is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2GU04 device contains two inverters with unbuffered outputs and performs the Boolean function Y = A.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

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활성

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활성

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활성

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기술 자료

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2개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드		날짜
*	데이터 시트	Dual Inverter Gate--SN74LVC2GU04 datasheet (Rev. N)			2013. 12. 12
	Application brief	Generate a Clock Signal from a Crystal Oscillator	PDF \| HTML		2020. 10. 8