SN74LVC2G240

활성

3상 출력을 지원하는 2채널, 1.65V~5.5V 인버터

지금 주문하기

데이터 시트

document-pdfAcrobat Dual Buffer/Driver With 3-State Outputs, SN74LVC2G240 datasheet (Rev. I) (영어)

SN74LVC2G240

활성

데이터 시트

지금 주문하기

제품 상세 정보

Technology family

LVC

Number of channels

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

DSBGA (YZP)

8

2.8125 mm² (— mm × — mm)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.6 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4.6 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

This dual buffer driver is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual buffer driver is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

filter

기타 인버팅 버퍼 및 드라이버 찾기

다운로드 스크립트와 함께 비디오 보기 비디오

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.

SN74AUP2G240

활성

3상 출력을 지원하는 2채널, 0.8V~3.6V 저전력 인버터 Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA

비교 대상 장치와 유사한 기능.

SN74AHCT240

활성

TTL 호환 CMOS 입력을 지원하는 8채널, 4.5V~5.5V 인버터 Voltage range 4.5V to 5.5V, average propagation delay 9ns, average drive strength 8mA

SN74ACT240

활성

TTL 호환 CMOS 입력 및 3상태 출력을 지원하는 8채널 4.5~5.5V 인버터 Voltage range 4.5V to 5.5V, average propagation delay 8ns, average drive strength 24mA

기술 자료

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2개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	Dual Buffer/Driver With 3-State Outputs, SN74LVC2G240 datasheet (Rev. I)			2013. 11. 25
	Application brief	High-Performance 16-bit PWM to 4- to 20-mA DAC for Field Transmitters			2020. 3. 26