SN74LVC1G79-Q1

활성

오토모티브 싱글 양극 에지 트리거 D형 플립플롭

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document-pdfAcrobat SN74LVC1G79-Q1 Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (영어) PDF | HTML

SN74LVC1G79-Q1

활성

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제품 상세 정보

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

Number of channels

1

Technology family

LVC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (max) (MHz)

150

IOL (max) (mA)

32

IOH (max) (mA)

-32

Supply current (max) (µA)

10

Features

Balanced outputs

Operating temperature range (°C)

-40 to 125

Rating

Automotive

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Max t_pd of 6 ns at 3.3 V and 50 pF load
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
I_off supports Partial-Power-Down Mode and Back-Drive Protection

Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
- ±4000-V Human-Body Model (HBM) ESD Classification Level 3A
- ±1000-V Charged-Device Model (CDM) ESD Classification Level C5
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Supports Down Translation to V_CC
Max t_pd of 6 ns at 3.3 V and 50 pF load
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
I_off supports Partial-Power-Down Mode and Back-Drive Protection

This automotive AEC-Q100 qualified single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This automotive AEC-Q100 qualified single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the level at the output.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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