SN74LVC1G0832

활성

단일 3 입력 양극 AND-OR 게이트

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document-pdfAcrobat SN74LVC1G0832 datasheet (Rev. D) (영어)

SN74LVC1G0832

활성

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제품 상세 정보

Technology family

LVC

Number of channels

1

Inputs per channel

3

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

1

Inputs per channel

3

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOT-23 (DBV)

6

8.12 mm² (2.9 mm × 2.8 mm)

DSBGA (YZP)

6

2.1875 mm² (— mm × — mm)

SOT-SC70 (DCK)

6

4.2 mm² (2 mm × 2.1 mm)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 5 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ @ 3.3 V)
Can Be Used in Three Combinations:
- AND-OR Gate
- AND Gate
- OR Gate
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments NanoFree Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Provides Down Translation to V_CC
Max t_pd of 5 ns at 3.3 V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Input Hysteresis Allows Slow Input
Transition and Better Switching Noise
Immunity at the Input
(V_hys = 250 mV Typ @ 3.3 V)
Can Be Used in Three Combinations:
- AND-OR Gate
- AND Gate
- OR Gate
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This device is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.

By tying one input to GND or V_CC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to V_CC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to V_CC (Y = A + C).

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This device is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.

By tying one input to GND or V_CC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to V_CC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to V_CC (Y = A + C).

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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