홈 로직 및 전압 변환 플립플롭, 래치 및 레지스터 D형 플립플롭
홈
로직 및 전압 변환
플립플롭, 래치 및 레지스터
D형 플립플롭

SN74LVC16374

활성

3상 출력을 지원하는 16비트 에지 트리거 D형 플립플롭

지금 주문하기
데이터 시트

SN74LVC16374

활성
데이터 시트 지금 주문하기

제품 상세 정보

Number of channels 16 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 16 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm)
  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA
    Per JEDEC Standard JESD-17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

  • Member of the Texas Instruments WidebusTM Family
  • EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Latch-Up Performance Exceeds 250 mA
    Per JEDEC Standard JESD-17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

    EPIC and Widebus are trademarks of Texas Instruments Incorporated.

This 16-bit edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVC16374 is characterized for operation from -40°C to 85°C.

This 16-bit edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74LVC16374 is characterized for operation from -40°C to 85°C.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.
SN74ALVCH16374 활성 3상 출력을 지원하는 16비트 에지 트리거 D형 플립플롭 Voltage range 1.65V to 3.6V, average propagation delay 3ns, average drive strength 24mA

기술 자료

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2개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs datasheet (Rev. B) 1995. 7. 1
애플리케이션 노트 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022. 12. 15

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