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Technology family LS Number of channels 1 Operating temperature range (°C) 0 to 70 Rating Catalog Supply current (max) (µA) 10000
Technology family LS Number of channels 1 Operating temperature range (°C) 0 to 70 Rating Catalog Supply current (max) (µA) 10000
PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm)
  • Designed Specifically for High-Speed:
    • Memory Decoders
    • Data Transmission Systems
  • 3 Enable Inputs to Simplify Cascading and/or Data Reception
  • Schottky-Clamped for High Performance

 

  • Designed Specifically for High-Speed:
    • Memory Decoders
    • Data Transmission Systems
  • 3 Enable Inputs to Simplify Cascading and/or Data Reception
  • Schottky-Clamped for High Performance

 

These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible.

The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design.

The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

 

These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible.

The 'LS138, SN54S138, and SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

All of these decoder/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and to simplify system design.

The SN54LS138 and SN54S138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS138 and SN74S138A are characterized for operation from 0°C to 70°C.

 

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.
SN74HC138 활성 3라인-8라인 디코더/디멀티플렉서 Voltage range 2V to 6V, average propagation delay 20ns, average drive strength 8mA
CD74AC138 활성 3라인~8라인 인버팅 디코더/디멀티플렉서 Voltage range 2V to 6V, average propagation delay 7ns, average drive strength 24mA

기술 자료

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* 데이터 시트 3-Line To 8-Line Decoders/Demultiplexers datasheet 1988. 3. 1

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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PDIP (N) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian

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