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Technology family HC Number of channels 2 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
Technology family HC Number of channels 2 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOIC (D) 16 59.4 mm² (9.9 mm × 6 mm)
  • Qualified for Automotive Applications
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to Ten LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 10 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • ESD Protection Level per AEC-Q100 Classification
    • 2000-V (H2) Human-Body Model
    • 200-V (M3) Machine Model
    • 1000-V (C5) Charged-Device Model

  • Qualified for Automotive Applications
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to Ten LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 10 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • ESD Protection Level per AEC-Q100 Classification
    • 2000-V (H2) Human-Body Model
    • 200-V (M3) Machine Model
    • 1000-V (C5) Charged-Device Model

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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기술 자료

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3개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 Dual 2-Line to 4-Line Decoder/Demultiplexer datasheet (Rev. B) 2008. 4. 24
Application brief Using Linear Interpolation to Estimate Specification Values PDF | HTML 2026. 4. 13
추가 자료 Automotive Logic Devices Brochure 2014. 8. 27

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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TSSOP (PW) 16 Ultra Librarian
SOIC (D) 16 Ultra Librarian

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