SN74ABT240A

활성

TTL 호환 CMOS 입력 및 3상태 출력을 지원하는 8채널 4.5V~5.5V 인버터

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document-pdfAcrobat Octal Buffers/Drivers With 3-State Outputs datasheet (Rev. I) (영어)

SN74ABT240A

활성

지금 주문하기

제품 상세 정보

Technology family

ABT

Number of channels

8

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

30000

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Technology family

ABT

Number of channels

8

IOL (max) (mA)

64

IOH (max) (mA)

-32

Supply current (max) (µA)

30000

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

PDIP (N)

20

228.702 mm² (24.33 mm × 9.4 mm)

SSOP (DB)

20

56.16 mm² (7.2 mm × 7.8 mm)

Typical V_OLP (Output Ground Bounce)
<1 V at V_CC = 5 V, T_A = 25°C
High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Typical V_OLP (Output Ground Bounce)
<1 V at V_CC = 5 V, T_A = 25°C
High-Drive Outputs (–32-mA I_OH, 64-mA I_OL)
I_off Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs.

The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs.

The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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