SN65DSI85-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With
the Following Results:
- Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
- Device HBM ESD Classification Level 3A
- Device CDM ESD Classification Level C6
- Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00
- Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
- Supports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
- Suitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp Color
- MIPI Front-End Configurable for Single-Channel or Dual-Channel DSI Configurations
- Output Configurable for Single-Link or Dual-Link LVDS
- Supports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating Modes
- Supports Two Single-Channel DSI to Two Single-Link LVDS Operating Mode
- LVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Mode
- LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
- 1.8-V Main VCC Power Supply
- Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
- LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
- Packaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package
The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY
receiver front-end
configuration with four lanes per channel operating at 1 Gbps per lane and a maximum input
bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and
converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from
25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces
with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm
HTQFP package with a
0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
관심 가지실만한 유사 제품
비교 대상 장치와 동일한 기능을 지원하는 핀 대 핀.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | SN65DSI85-Q1 Automotive Dual-Channel MIPI DSI to Dual-Link LVDS Bridge datasheet (Rev. B) | PDF | HTML | 2018. 6. 28 | |
| 애플리케이션 노트 | Troubleshooting SN65DSI8x - Tips and Tricks | 2018. 8. 27 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
SN65DSI85Q1-EVM — 듀얼 채널 MIPI® DSI-to-듀얼 링크 FlatLink™ LVDS 브리지 평가 모듈
TIDA-01453 — 차량용 인포테인먼트 헤드 유닛을 위한 MIPI® DSI-ODDI/LVDS 브리지 레퍼런스 설계
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HTQFP (PAP) | 64 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.