LP2998
- AEC-Q100 Test Guidance with the following results
(SO PowerPAD-8):- Device HBM ESD Classification Level H1C
- Junction Temperature Range –40°C to 125°C
- 1.35 V Minimum VDDQ
- Source and Sink Current
- Low Output Voltage Offset
- No External Resistors Required
- Linear Topology
- Suspend to Ram (STR) Functionality
- Low External Component Count
- Thermal Shutdown
The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQ min of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs.
An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. When SD is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | LP2998/LP2998-Q1 DDR Termination Regulator datasheet (Rev. K) | PDF | HTML | 2014. 8. 20 | |
| 애플리케이션 노트 | DDR VTT Power Solutions: A Competitive Analysis (Rev. A) | 2020. 7. 9 | |||
| 애플리케이션 노트 | Limiting DDR Termination Regulators’ Inrush Current | 2016. 8. 23 | |||
| 애플리케이션 노트 | AN-1254 DDR-SDRAM Termination Simplified Using a Linear Regulator (Rev. A) | 2013. 5. 6 | |||
| 애플리케이션 노트 | Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs | 2010. 4. 28 | |||
| 애플리케이션 노트 | Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices | 2010. 4. 20 | |||
| 애플리케이션 노트 | Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) | 2010. 3. 31 | |||
| 애플리케이션 노트 | 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) | 2010. 3. 26 | |||
| 애플리케이션 노트 | TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers | 2010. 3. 26 | |||
| 애플리케이션 노트 | Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs | 2010. 3. 26 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LP2998EVAL — LP2998용 평가 보드
The LP2998 evaluation board is designed to provide the design Engineer with a fully functional prototype system in which to evaluate the LP2998 in both a static environment and with a complete memory system.
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| HSOIC (DDA) | 8 | Ultra Librarian |
| SOIC (D) | 8 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.