LMK04714-Q1

활성

오토모티브 초저잡음 3.2GHz, JESD204B 및 JESD204C 이중 루프 클록 지터 클리너

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데이터 시트

document-pdfAcrobat LMK04714-Q1 Automotive Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner datasheet (영어) PDF | HTML

LMK04714-Q1

활성

지금 주문하기

제품 상세 정보

Number of input channels

3

Number of outputs

15

RMS jitter (fs)

54

Features

0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI

Output frequency (max) (MHz)

3255

Output type

CML, HSDS, LVCMOS, LVDS, LVPECL

Input type

HCSL, LVCMOS, LVDS, LVPECL

Operating temperature range (°C)

-40 to 125

Number of input channels

3

Number of outputs

15

RMS jitter (fs)

54

Features

0 Delay, Integrated VCO, JESD204B, Loss of signal detection, Manual/auto switch, Programmable Delay, SPI

Output frequency (max) (MHz)

3255

Output type

CML, HSDS, LVCMOS, LVDS, LVPECL

Input type

HCSL, LVCMOS, LVDS, LVPECL

Operating temperature range (°C)

-40 to 125

HTQFP (PAP)

64

144 mm² (12 mm × 12 mm)

AEC-Q100 Grade 1: –40°C to 125°C
Maximum clock output frequency: 3255 MHz
Multi-mode: dual PLL, single PLL, and clock distribution
6-GHz external VCO or distribution input
Ultra-low noise, at 2500 MHz:
- 54-fs RMS jitter (12 kHz to 20 MHz)
- 64-fs RMS jitter (100 Hz to 20 MHz)
- –157.6-dBc/Hz noise floor
Ultra-low noise, at 3200 MHz:
- 61-fs RMS jitter (12 kHz to 20 MHz)
- 67-fs RMS jitter (100 Hz to 100 MHz)
- –156.5-dBc/Hz noise floor
PLL2
- PLL FOM of –230 dBc/Hz
- PLL 1/f of –128 dBc/Hz
- Phase detector rate up to 320 MHz
- Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
Up to 14 differential device clocks
- CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
Up to 1 buffered VCXO/XO output
- LVPECL, LVDS, 2xLVCMOS programmable
1-1023 CLKOUT integer divider
1-8191 SYSREF integer divider
25-ps step analog delay for SYSREF clocks
Digital delay and dynamic digital delay for device clocks and SYSREF
Holdover mode with PLL1
0-delay with PLL1 or PLL2
High Reliability
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability

AEC-Q100 Grade 1: –40°C to 125°C
Maximum clock output frequency: 3255 MHz
Multi-mode: dual PLL, single PLL, and clock distribution
6-GHz external VCO or distribution input
Ultra-low noise, at 2500 MHz:
- 54-fs RMS jitter (12 kHz to 20 MHz)
- 64-fs RMS jitter (100 Hz to 20 MHz)
- –157.6-dBc/Hz noise floor
Ultra-low noise, at 3200 MHz:
- 61-fs RMS jitter (12 kHz to 20 MHz)
- 67-fs RMS jitter (100 Hz to 100 MHz)
- –156.5-dBc/Hz noise floor
PLL2
- PLL FOM of –230 dBc/Hz
- PLL 1/f of –128 dBc/Hz
- Phase detector rate up to 320 MHz
- Two integrated VCOs: 2440 to 2600 MHz and 2945 to 3255 MHz
Up to 14 differential device clocks
- CML, LVPECL, LCPECL, HSDS, LVDS, and 2xLVCMOS programmable outputs
Up to 1 buffered VCXO/XO output
- LVPECL, LVDS, 2xLVCMOS programmable
1-1023 CLKOUT integer divider
1-8191 SYSREF integer divider
25-ps step analog delay for SYSREF clocks
Digital delay and dynamic digital delay for device clocks and SYSREF
Holdover mode with PLL1
0-delay with PLL1 or PLL2
High Reliability
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability

The LMK04714-Q1 is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.

The LMK04714-Q1 is a high performance clock conditioner with JEDEC JESD204B/C support for space applications.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B/C converters or other logic devices using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B/C applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

This device can be configured for operation in dual PLL, single PLL, or clock distribution modes with or without SYSREF generation or reclocking. PLL2 may operate with either internal or external VCO.

The high performance combined with features like the ability to trade off between power and performance, dual VCOs, dynamic digital delay, and holdover allows to provide flexible high performance clocking trees.

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상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드		날짜
*	데이터 시트	LMK04714-Q1 Automotive Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner datasheet	PDF \| HTML		2023. 10. 5

설계 및 개발

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지원 소프트웨어

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

텍사스 인스트루먼트 클록 및 신시사이저(TICS) Pro 소프트웨어는 다음 접두사를 사용하여 제품 번호의 평가 모듈(EVM)을 프로그래밍하는 데 사용됩니다. CDC, LMK 및 LMX. 이러한 제품에는 위상 동기 루프 및 전압 제어 오실레이터(PLL+VCO), 신시사이저 및 클로킹 디바이스가 포함되어 있습니다.

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