DS90UH928Q-Q1
- Qualified for Automotive Applications AEC-Q100
- Device Temperature Grade 2: –40°C to +105°C Ambient Operating Temperature Range
- Device HBM ESD Classification Level ±8 kV
- Device CDM ESD Classification Level C6
- Integrated HDCP Cipher Engine with On-Chip Key Storage
- Supports HDCP Repeater Application
- Bidirectional Control Channel Interface with I2C Compatible Serial Control Bus
- Low EMI FPD-Link Video Output
- Supports High Definition (720p) Digital Video
- RGB888 + VS, HS, DE and I2S Audio Supported
- 5 MHz to 85 MHz Pixel Clock Support
- Up to 4 I2S Digital Audio Outputs for Surround Sound Applications
- 4 Bidirectional GPIO Channels with 2 Dedicated Pins
- Single 3.3 V supply with 1.8 V or 3.3 V Compatible LVCMOS I/O Interface
- AC-Coupled STP Interconnect Up to 10 Meters
- DC-Balanced and Scrambled Data with Embedded Clock
- Adaptive Cable Equalization
- Image Enhancement (White Balance & Dithering) and Internal Pattern Generation
- Backward Compatible Modes
The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
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기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90UH928Q-Q1 5 MHz to 85 MHz 24-bit Color FPD-Link III to FPD-Link Deserializer With HDCP datasheet (Rev. C) | PDF | HTML | 2016. 5. 16 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS90UB928QEVM — DS90UB928QEVM FPD-Link III 디시리얼라이저 평가 모듈
DS90UH928QEVM — DS90UH928QEVM FPD-Link III 디시리얼라이저 평가 모듈
The Texas Instruments DS90UH928QEVM evaluation module (EVM) helps system designers evaluate the operation and performance of the DS90UH928Q 5MHz-85MHz FPD-Link III Deserializer (DES). The device translates a high-speed serialized FPD-Link III interface transported over a single shielded twisted (...)
ALP — Analog LaunchPad Framework Utility
ALP-PROFILE-UPDATE — Analog LaunchPad Profile Update Software
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RHS) | 48 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.