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Technology family CD4000 Bits (#) 4 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family CD4000 Bits (#) 4 Rating Catalog Operating temperature range (°C) -55 to 125
TSSOP (PW) 16 32 mm² (5 mm × 6.4 mm) SOIC (DW) 16 106.09 mm² (10.3 mm × 10.3 mm) SOP (NS) 16 79.56 mm² (10.2 mm × 7.8 mm) PDIP (N) 16 181.42 mm² (19.3 mm × 9.4 mm)
  • 24 flip-flop stages - - counts from 20 to 224
  • Last 16 stages selectable by BCD select code
  • Bypass input allows bypassing first 8 stages
  • On-chip RC oscillator provision
  • Clock inhibit input
  • Schmitt-trigger in clock line permits operation with very long rise and fall times
  • On-chip monostable output provision
  • Typical fCL = 3 MHz at VDD = 10 V
  • Test mode allows fast test sequence
  • Set and reset inputs
  • Capable of driving two low power TTL loads, one lower-power Schottky load, or two HTL loads over the rated temperature range
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • 24 flip-flop stages - - counts from 20 to 224
  • Last 16 stages selectable by BCD select code
  • Bypass input allows bypassing first 8 stages
  • On-chip RC oscillator provision
  • Clock inhibit input
  • Schmitt-trigger in clock line permits operation with very long rise and fall times
  • On-chip monostable output provision
  • Typical fCL = 3 MHz at VDD = 10 V
  • Test mode allows fast test sequence
  • Set and reset inputs
  • Capable of driving two low power TTL loads, one lower-power Schottky load, or two HTL loads over the rated temperature range
  • Standardized, symmetrical output characteristics
  • 100% tested for quiescent current at 20 V
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

CD4536B is a programmable timer consisting of 24 ripple-binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using combinations of these capabilities.

A logic 1 on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10K ohms or higher, disables the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and control its pulse width.

A fast test mode is enabled by a logic 1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence.

The CD4536B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4536B is a programmable timer consisting of 24 ripple-binary counter stages. The salient feature of this device is its flexibility. The device can count from 1 to 224 or the first 8 stages can be bypassed to allow an output, selectable by a 4-bit code, from any one of the remaining 16 stages. It can be driven by an external clock or an RC oscillator that can be constructed using on-chip components. Input IN1 serves as either the external clock input or the input to the on-chip RC oscillator. OUT1 and OUT2 are connection terminals for the external RC components. In addition, an on-chip monostable circuit is provided to allow a variable pulse width output. Various timing functions can be achieved using combinations of these capabilities.

A logic 1 on the 8-BYPASS input enables a bypass of the first 8 stages and makes stage 9 the first counter stage of the last 16 stages. Selection of 1 of 16 outputs is accomplished by the decoder and the BCD inputs A, B, C and D. MONO IN is the timing input for the on-chip monostable oscillator. Grounding of the MONO IN terminal through a resistor of 10K ohms or higher, disables the one-shot circuit and connects the decoder directly to the DECODE OUT terminal. A resistor to VDD and a capacitor to ground from the MONO IN terminal enables the one-shot circuit and control its pulse width.

A fast test mode is enabled by a logic 1 on 8-BYPASS, SET, and RESET. This mode divides the 24-stage counter into three 8-stage sections to facilitate a fast test sequence.

The CD4536B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (DW, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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비교 대상 장치와 유사한 기능.
TPL5010 활성 워치독 기능과 수동 리셋을 지원하는 나노 전력 시스템 타이머 Watchdog timer

기술 자료

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* 데이터 시트 CD4536B Types datasheet (Rev. B) 2003. 3. 12

설계 및 개발

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평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

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TSSOP (PW) 16 Ultra Librarian
SOIC (DW) 16 Ultra Librarian
SOP (NS) 16 Ultra Librarian
PDIP (N) 16 Ultra Librarian

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