ADC12DJ800

활성

JESD204C 인터페이스를 지원하는 듀얼 채널, 12비트, 800MSPS 아날로그-디지털 컨버터(ADC)

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데이터 시트

document-pdfAcrobat ADC12xJ800 Quad, Dual, Single Channel, 800MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) (영어) PDF | HTML

ADC12DJ800

활성

지금 주문하기

제품 상세 정보

Sample rate (max) (Msps)

800

Resolution (Bits)

12

Number of input channels

2

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

6000

Features

Ultra High Speed

Rating

Catalog

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

1110

Architecture

Folding Interpolating

SNR (dB)

57.6

ENOB (Bits)

9

SFDR (dB)

62

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

800

Resolution (Bits)

12

Number of input channels

2

Interface type

JESD204B, JESD204C

Analog input BW (MHz)

6000

Features

Ultra High Speed

Rating

Catalog

Peak-to-peak input voltage range (V)

0.8

Power consumption (typ) (mW)

1110

Architecture

Folding Interpolating

SNR (dB)

57.6

ENOB (Bits)

9

SFDR (dB)

62

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

FCCSP (AAV)

144

100 mm² (10 mm × 10 mm)

ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 800MSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
Performance specifications (–1dBFS):
- SNR (97 MHz): 57.6dBFS
- ENOB (97 MHz): 9 Bits
- SFDR (97 MHz): 62dBFS
- Noise floor (–20dBFS): –146.1dBFS/Hz
Full-scale input voltage: 800mVPP-DIFF
Full-power input bandwidth: GHz
JESD204C Serial data interface:
- Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2GHz)
SYSREF Windowing eases synchronization
Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
Timestamp input and output for pulsed systems
Power consumption (800MSPS):
- Quad Channel: 415mW / channel
- Dual channel: 555mW / channel
- Single channel: 830mW
Power supplies: 1.1V, 1.9V

ADC Core:
- Resolution: 12 Bit
- Maximum sampling rate: 800MSPS
- Non-interleaved architecture
- Internal dither reduces high-order harmonics
Performance specifications (–1dBFS):
- SNR (97 MHz): 57.6dBFS
- ENOB (97 MHz): 9 Bits
- SFDR (97 MHz): 62dBFS
- Noise floor (–20dBFS): –146.1dBFS/Hz
Full-scale input voltage: 800mVPP-DIFF
Full-power input bandwidth: GHz
JESD204C Serial data interface:
- Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
- Maximum baud-rate: 17.16Gbps
- 64B/66B and 8B/10B encoding modes
- Subclass-1 support for deterministic latency
- Compatible with JESD204B receivers
Optional internal sampling clock generation
- Internal PLL and VCO (7.2–8.2GHz)
SYSREF Windowing eases synchronization
Four clock outputs simplify system clocking
- Reference clocks for FPGA or adjacent ADC
- Reference clock for SerDes transceivers
Timestamp input and output for pulsed systems
Power consumption (800MSPS):
- Quad Channel: 415mW / channel
- Dual channel: 555mW / channel
- Single channel: 830mW
Power supplies: 1.1V, 1.9V

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12xJ800 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800 ideally suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

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3개 모두 보기

상위 문서	유형	직함	형식 옵션
*	데이터 시트	ADC12xJ800 Quad, Dual, Single Channel, 800MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A)	PDF \| HTML	2024. 10. 18
	애플리케이션 노트	Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends	PDF \| HTML	2025. 3. 28
	애플리케이션 노트	Evaluating High-Speed, RF ADC Converter Front-end Architectures	PDF \| HTML	2025. 3. 26

설계 및 개발

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평가 보드

ADC12QJ1600EVM — ADC12QJ1600 - JESD204C 인터페이스를 지원하는 쿼드 채널, 12비트, 1.6GSPS ADC용 평가 모듈

ADC12QJ1600 평가 모듈(EVM)은 고속 ADC(아날로그-디지털 컨버터) ADC12QJ1600-Q1 제품군을 평가하기 위해 설계되었습니다. 이 EVM에는 JESD204B 인터페이스를 지원하는 12비트, 쿼드 채널 1.6GSPS ADC인 ADC12QJ1600-Q1이 장착되어 있어 12비트 제품군의 모든 샘플 레이트와 싱글, 듀얼 및 쿼드 채널 차량용 또는 산업용 등급 장치를 평가할 수 있습니다.

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