이 제품의 최신 버전이 있습니다

open-in-new 대안 비교
비교 대상 장치와 유사한 기능.
ADC3910S065 활성 10비트, 1채널, 65MSPS ADC 단일 클록 사이클 지연 시간 최대 16배 데시메이션 디지털 비교기 Higher sampling rate and smaller package size

제품 상세 정보

Sample rate (max) (Msps) 40 Resolution (Bits) 10 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 400 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 55.5 Architecture Pipeline SNR (dB) 58.7 ENOB (Bits) 9.6 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 40 Resolution (Bits) 10 Number of input channels 1 Interface type Parallel CMOS, TTL Analog input BW (MHz) 400 Features Low Power Rating Automotive Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 55.5 Architecture Pipeline SNR (dB) 58.7 ENOB (Bits) 9.6 SFDR (dB) 80 Operating temperature range (°C) -40 to 85 Input buffer No
TSSOP (PW) 28 62.08 mm² (9.7 mm × 6.4 mm)
  • Single +3.0V Operation
  • Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • AEC-Q100 Grade 3 Qualified
  • 28-Pin TSSOP Package

Key Specifications

  • Resolution: 10 Bits
  • Conversion Rate: 40 MSPS
  • Full Power Bandwidth: 400 MHz
  • DNL: ±0.3 LSB typ)
  • SNR (fIN = 11 MHz): 59.6 dB (typ)
  • SFDR (fIN = 11 MHz): -80 dB (typ)
  • Power Consumption, 40 MHz: 55.5 mW

All trademarks are the property of their respective owners.

  • Single +3.0V Operation
  • Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
  • 400 MHz −3 dB Input Bandwidth
  • Low Power Consumption
  • Standby Mode
  • On-Chip Reference and Sample-and-Hold Amplifier
  • Offset Binary or Two’s Complement Data Format
  • Separate Adjustable Output Driver Supply to Accommodate 2.5V and 3.3V Logic Families
  • AEC-Q100 Grade 3 Qualified
  • 28-Pin TSSOP Package

Key Specifications

  • Resolution: 10 Bits
  • Conversion Rate: 40 MSPS
  • Full Power Bandwidth: 400 MHz
  • DNL: ±0.3 LSB typ)
  • SNR (fIN = 11 MHz): 59.6 dB (typ)
  • SFDR (fIN = 11 MHz): -80 dB (typ)
  • Power Consumption, 40 MHz: 55.5 mW

All trademarks are the property of their respective owners.

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 55.5 mW at 40 MSPS, including the reference current. The Standby feature reduces power consumption to just 13.5 mW.

The differential inputs provide a full scale selectable input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the possibility of a single-ended input. Full use of the differential input is recommended for optimum performance. An internal +1.2V precision bandgap reference is used to set the ADC full-scale range, and also allows the user to supply a buffered referenced voltage for those applications requiring increased accuracy. The output data format is user choice of offset binary or two’s complement.

The ADC10040Q runs on an Automotive Grade Flow and is AEC-Q100 Grade 3 Qualified.

This device is available in the 28-lead TSSOP package and will operate over the industrial temperature range of −40°C to +85°C.

다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
2개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 ADC10040/ADC10040Q 10-Bit, 40 MSPS, 3V, 55.5 mW A/D Converter datasheet (Rev. M) 2013. 4. 18
사용 설명서 ADC10040/65/80 10-Bit, 40/65/80 MSPS, 3 Volt, 55.5/68.5/78.6 mW ADC User Guide 2012. 2. 20

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (PW) 28 Ultra Librarian

주문 및 품질

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상