홈 마이크로컨트롤러(MCU) 및 프로세서 마이크로프로세서 및 DSP 오디오 및 레이더 DSP SoC
홈
마이크로컨트롤러(MCU) 및 프로세서
마이크로프로세서 및 DSP
오디오 및 레이더 DSP SoC

66AK2G12

활성

고성능 멀티코어 DSP+Arm -1x Arm A15 코어, 1x C66x DSP 코어

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66AK2G12

활성
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CPU 1 Arm Cortex-A15 Frequency (MHz) 600, 1000 Coprocessors C66x DSP Display type 1 LCD PCIe 1 PCIe Gen 2 Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Secure boot, Secure storage Rating Catalog Operating temperature range (°C) -40 to 125
CPU 1 Arm Cortex-A15 Frequency (MHz) 600, 1000 Coprocessors C66x DSP Display type 1 LCD PCIe 1 PCIe Gen 2 Hardware accelerators Industrial communications subsystem, Programable real-time unit, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Secure boot, Secure storage Rating Catalog Operating temperature range (°C) -40 to 125
FCCSP (ABY) 625 441 mm² (21 mm × 21 mm)
  • Processor cores:
  • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz
    • Supports full Implementation of Armv7-A architecture instruction set
    • Integrated SIMDv2 (Arm® Neon™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 512KB of L2 memory
    • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
    • Parity protection for L1 program memory
    • Global Timebase Counter (GTC)
      • 64-Bit free-running counter that provides timebase for Arm A15 internal timers
      • Compliant to Armv7 MPCore Architecture for Generic Timers
  • C66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHz
    • Fully object-code compatible With C67x+ and C64x+ cores
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 1024KB of L2 configurable as L2 RAM or cache
    • Error detection for L1 program memory
    • ECC for L1 data memory
    • ECC for L2 data memory
  • Industrial subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:
    • Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:
      • 16KB of program memory With ECC
      • 8KB of data memory With ECC
      • CRC32 and CRC16 hardware accelerator
      • 20 × enhanced GPIO
      • Serial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulation
      • Scratch pad and XFR direct connect
    • 64KB of general-purpose memory With ECC
    • One Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocols
    • Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®
    • Built-In industrial Ethernet 64-Bit timer
    • Built-In enhanced capture module (eCAP)
  • Memory subsystem:
  • Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAM
    • Provides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x Access
    • Supports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 1066 MT/s
    • Supports 4-GB memory address range
    • Supports 32-Bit SDRAM data bus with 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM data bus without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selects
    • Supports NOR, Muxed-NOR, SRAM
    • Supports general-purpose memory-port expansion with the following modes:
      • Asynchronous read and write access
      • Asynchronous read page access (4-, 8-, 16-Word16)
      • Synchronous read and write access
      • Synchronous read burst access without wrap capability (4-, 8-, 16-Word16)
  • Network Subsystem (NSS):
  • Ethernet MAC (EMAC) subsystem
    • One-port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps full duplex
    • Supports 10-, 100-Mbps half duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum frame size 2016 Bytes (2020 Bytes with VLAN)
    • Eight priority level QOS support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)
    • CPTS module with timestamping support for IEEE 1588v2
    • DSCP priority mapping (IPv4 and IPv6)
    • MDIO module for PHY management
    • Enhanced statistics collection
  • Navigator Subsystem (NAVSS)
    • Built-In packet DMA controller for optimized network processing
    • Built-In Queue Manager (QM) for optimized network processing
      • Supports up to 128 queues
      • 2048 buffers supported in internal queue RAM
  • Crypto Engine (SA) supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block data encryption supported through hardware cores
      • AES with 128-, 192-, and 256-Bit Key supports
      • DES and 3DES with 1, 2, or 3 Different Key support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) with elliptic curve cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC operation through hardware core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports one video pipe with in-loop scaling, color space
  • Conversion and background color overlay
  • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported display interfaces:
    • MIPI® DPI 2.0 parallel interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-loop scaling capability
  • LCD interface supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)
  • Up to 8 stereo streams (16 audio channels)
  • Automatically sensing / detection of input sample frequencies
  • Attenuation of sampling clock jitter
  • 16-, 18-, 20-, 24-Bit data input/output
  • Audio sample rates from 8 kHz to 216 kHz
  • Input/output sampling ratios from 16:1 to 1:16
  • Group mode, where multiple ASRC blocks use the same timing loop for input or output
  • Linear phase FIR filter
  • Controllable soft mute
  • Independent clock generator, and rate and stamp generator, for each input and output clock zone
  • Separate DMA events for input and output, for each channel and group
  • High-speed serial interfaces:
  • PCI Express® 2.0 port with integrated PHY:
    • Single lane Gen2-compliant port
    • Root Complex (RC) and End Point (EP) modes
  • Up to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:
    • Dual-role-device (DRD) Capability with:
      • USB 2.0 peripheral (or device) at
        HS (480Mbps) and FS (12Mbps) speeds
      • USB 2.0 host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) speeds
      • USB 2.0 static peripheral and static host operations
    • xHCI controller with the following features:
      • Compatible to the xHCI specification (revision 1.1) in host mode
      • All modes of transfer (control, bulk, interrupt, and isochronous)
      • 15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)
  • Flash media interfaces:
  • QSPI™ with XIP and up to four chip selects, supports:
    • Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM buffer with ECC
    • High speed read data capture mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standards
    • MMC0 supports 3.3-V I/O for:
      • SD DS and HS mode
      • eMMC mode HS-SDR
        up to 48 MHz
    • MMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus width
  • Audio peripherals:
  • Three Multichannel Audio Serial Port (McASP) peripherals
    • Transmit and receive clocks up to 50 MHz
    • Two independent clock zones and independent transmit and receive clocks per McASP
    • Up to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectively
    • Supports TDM, I2S, and similar formats
    • Supports DIT mode
    • Built-In FIFO buffers for optimized system traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and receive clocks up to 50 MHz
    • Two clock zones and two serial-data pins
    • Supports TDM, I2S, and similar formats
  • Real-time control interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:
    • Dedicated 16-Bit Time-Base with Period and Frequency Control
    • Two independent PWM outputs with single edge operation
    • Two independent PWM outputs with dual-edge symmetric operation
    • One independent PWM output with dual-edge asymmetric operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports one capture input or one auxiliary PWM output configuration options
    • 4-Event time-stamp registers (Each 32-Bits)
    • Interrupt on either of the four events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:
    • Quadrature decoding
    • Position counter and control unit for position measurement
    • Unit time base for speed and frequency measurement
  • General connectivity:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) protocol
    • Bit rates up to 1 Mbps
    • Dual clock source
    • ECC protection for message RAM
  • One Media Local Bus (MLB)
    • Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB® Physical layer specification v4.2
    • Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)
    • Supports 3-wire MOST 150 protocol
  • Three Inter-Integrated Circuit (I2C) interfaces, each supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) modes
    • 7-Bit addressing mode
    • Supports EEPROM size up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), each supports:
    • Operates at up to 50 MHz in master mode and 25 MHz in slave mode
    • Two chip selects
  • Three UART interfaces
    • All UARTs are 16C750-compatible and operate at up to 3M baud
    • UART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signals
    • UART1 and UART2 are 4-pin interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs muxed with other interfaces
    • Can be configured as interrupt pins
  • Timers and miscellaneous modules:
  • Seven 64-Bit timers:
    • Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit timers are shared for general purposes
    • Each 64-Bit timer can be configured as two individual 32-Bit timers
    • One 64-Bit timer dedicated for PMMC
    • Two timers input/output pin pairs
  • Interprocessor communication with:
    • Message manager to facilitate multiprocessor access to the PMMC:
      • Provides hardware acceleration for pushing and popping messages to/from logical queues
      • Supports up to 64 queues and 128 messages
    • Semaphore module with up to 64 independent semaphores and 16 masters (device cores)
  • EDMA with 128 (2 × 64) channels and
    1024 (2 × 512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) devices
    • Supports secure boot
    • Supports customer secondary keys
    • 4KB of One-Time Programmable (OTP) ROM for customer keys
  • Power management
    • Integrated Power Management Microcontroller (PMMC) technology
  • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
  • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Industrial Extended)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)
  • Processor cores:
  • Arm® Cortex®-A15 microprocessor unit (Arm A15) subsystem at up to 1000 MHz
    • Supports full Implementation of Armv7-A architecture instruction set
    • Integrated SIMDv2 (Arm® Neon™ Technology) and VFPv4 (Vector Floating Point)
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 512KB of L2 memory
    • Error Correction Code (ECC) protection for L1 data memory ECC for L2 memory
    • Parity protection for L1 program memory
    • Global Timebase Counter (GTC)
      • 64-Bit free-running counter that provides timebase for Arm A15 internal timers
      • Compliant to Armv7 MPCore Architecture for Generic Timers
  • C66x fixed- and floating-point VLIW DSP subsystem at up to 1000 MHz
    • Fully object-code compatible With C67x+ and C64x+ cores
    • 32KB of L1 program memory
    • 32KB of L1 data memory
    • 1024KB of L2 configurable as L2 RAM or cache
    • Error detection for L1 program memory
    • ECC for L1 data memory
    • ECC for L2 data memory
  • Industrial subsystem:
  • Up to Two Programmable Real-Time Unit and Industrial Communication Subsystems (PRU-ICSS), each supports:
    • Two Programmable Real-Time Units (PRUs) with enhanced multiplier and accumulator, each PRU supports:
      • 16KB of program memory With ECC
      • 8KB of data memory With ECC
      • CRC32 and CRC16 hardware accelerator
      • 20 × enhanced GPIO
      • Serial Capture Unit (SCU), supporting direct connection, 16-bit parallel capture, 28-bit shift, MII_RT, EnDat 2.2 protocol and Sigma-Delta demodulation
      • Scratch pad and XFR direct connect
    • 64KB of general-purpose memory With ECC
    • One Ethernet MII_RT module with two MII ports configurable for connection with each PRU; supports multiple industrial communication protocols
    • Industrial Ethernet Peripheral (IEP) to manage and generate industrial Ethernet functions
    • Built-In Universal Asynchronous Receiver and Transmitter (UART) 16550, with a dedicated 192-MHz clock to support 12-Mbps PROFIBUS®
    • Built-In industrial Ethernet 64-Bit timer
    • Built-In enhanced capture module (eCAP)
  • Memory subsystem:
  • Multicore Shared Memory Controller (MSMC) with 1024KB of shared L2 RAM
    • Provides high-performance interconnect to internal shared SRAM and DDR EMIF for both Arm A15 and C66x Access
    • Supports Arm I/O coherency where Arm A15 is cache coherent to other system masters accessing the MSMC-SRAM or DDR EMIF
    • Supports ECC on SRAM
  • Up to 36-Bit DDR External Memory Interface (EMIF)
    • Supports DDR3L at up to 1066 MT/s
    • Supports 4-GB memory address range
    • Supports 32-Bit SDRAM data bus with 4-bit ECC
    • Supports 16-Bit and 32-Bit SDRAM data bus without ECC
  • General-Purpose Memory Controller (GPMC)
    • Flexible 8- and 16-Bit asynchronous memory interface with up to four chip selects
    • Supports NOR, Muxed-NOR, SRAM
    • Supports general-purpose memory-port expansion with the following modes:
      • Asynchronous read and write access
      • Asynchronous read page access (4-, 8-, 16-Word16)
      • Synchronous read and write access
      • Synchronous read burst access without wrap capability (4-, 8-, 16-Word16)
  • Network Subsystem (NSS):
  • Ethernet MAC (EMAC) subsystem
    • One-port Gigabit Ethernet: RMII, MII, RGMII
    • Supports 10-, 100-, 1000-Mbps full duplex
    • Supports 10-, 100-Mbps half duplex
    • Supports Ethernet Audio Video Bridging (eAVB)
    • Maximum frame size 2016 Bytes (2020 Bytes with VLAN)
    • Eight priority level QOS support (802.1p)
    • IEEE 1588v2 (2008 Annex D, Annex E, and
      Annex F) to facilitate Audio Video Bridging 802.1AS Precision Time Protocol (PTP)
    • CPTS module with timestamping support for IEEE 1588v2
    • DSCP priority mapping (IPv4 and IPv6)
    • MDIO module for PHY management
    • Enhanced statistics collection
  • Navigator Subsystem (NAVSS)
    • Built-In packet DMA controller for optimized network processing
    • Built-In Queue Manager (QM) for optimized network processing
      • Supports up to 128 queues
      • 2048 buffers supported in internal queue RAM
  • Crypto Engine (SA) supports:
    • Crypto Function Library for AES, DES, 3DES, SHA1, MD5, SHA2-224 and SHA2-256 Operations
    • Block data encryption supported through hardware cores
      • AES with 128-, 192-, and 256-Bit Key supports
      • DES and 3DES with 1, 2, or 3 Different Key support
    • Programmable Mode Control Engine (MCE)
    • Public Key Accelerator (PKA) with elliptic curve cryptography
    • Elliptic Curve Diffie–Hellman (ECDH) based key exchange and digital signature (ECDSA) applications
    • Authentication for SHA1, MD5, SHA2-224 and SHA2-256
    • Keyed HMAC operation through hardware core
    • True Random Number Generator (TRNG)
  • Display Subsystem:
  • Supports one video pipe with in-loop scaling, color space
  • Conversion and background color overlay
  • Input data format: BITMAP, RGB16, RGB24, RGB32, ARGB16, ARGB32, YUV420, YUV422, and RGB565-A8
  • Supported display interfaces:
    • MIPI® DPI 2.0 parallel interface
    • RFBI (MIPI-DBI 2.0) up to QVGA at 30fps
    • BT.656 4:2:2
    • BT.1120 4:2:2 up to 1920 × 1080 at 30fps
  • In-loop scaling capability
  • LCD interface supports:
    • Active Matrix (TFT)
    • Passive Matrix (STN)
    • Grayscale
    • TDM
    • AC Bias Control
    • Dither
    • CPR
  • Asynchronous Audio Sample Rate Converter (ASRC)
  • High performance asynchronous sample rate converter with 140 dB Signal-to-Noise (SNR)
  • Up to 8 stereo streams (16 audio channels)
  • Automatically sensing / detection of input sample frequencies
  • Attenuation of sampling clock jitter
  • 16-, 18-, 20-, 24-Bit data input/output
  • Audio sample rates from 8 kHz to 216 kHz
  • Input/output sampling ratios from 16:1 to 1:16
  • Group mode, where multiple ASRC blocks use the same timing loop for input or output
  • Linear phase FIR filter
  • Controllable soft mute
  • Independent clock generator, and rate and stamp generator, for each input and output clock zone
  • Separate DMA events for input and output, for each channel and group
  • High-speed serial interfaces:
  • PCI Express® 2.0 port with integrated PHY:
    • Single lane Gen2-compliant port
    • Root Complex (RC) and End Point (EP) modes
  • Up to two USB 2.0 High-Speed dual-role ports with Integrated PHYs, support:
    • Dual-role-device (DRD) Capability with:
      • USB 2.0 peripheral (or device) at
        HS (480Mbps) and FS (12Mbps) speeds
      • USB 2.0 host at HS (480Mbps),
        FS (12Mbps), and LS (1.5Mbps) speeds
      • USB 2.0 static peripheral and static host operations
    • xHCI controller with the following features:
      • Compatible to the xHCI specification (revision 1.1) in host mode
      • All modes of transfer (control, bulk, interrupt, and isochronous)
      • 15 transmit (TX), 15 receive (RX) endpoints (EPs), and one bidirectional endpoint (EP0)
  • Flash media interfaces:
  • QSPI™ with XIP and up to four chip selects, supports:
    • Memory-mapped direct mode of operation for performing FLASH data transfers and executing code from FLASH memory (XIP)
    • Supports up to 96 MHz
    • Internal SRAM buffer with ECC
    • High speed read data capture mechanism
  • Two Multimedia Card (MMC) and Secure Digital (SD) ports
    • Supports JEDEC JESD84 v4.5-A441 and SD3.0 physical layer with SDA3.00 standards
    • MMC0 supports 3.3-V I/O for:
      • SD DS and HS mode
      • eMMC mode HS-SDR
        up to 48 MHz
    • MMC1 supports 1.8-V I/O modes for eMMC, including HS-SDR and DDR at up to 48 MHz with 4- and 8-Bit bus width
  • Audio peripherals:
  • Three Multichannel Audio Serial Port (McASP) peripherals
    • Transmit and receive clocks up to 50 MHz
    • Two independent clock zones and independent transmit and receive clocks per McASP
    • Up to 16-, 10-, 6-serial data pins for McASP0, McASP1, and McASP2, respectively
    • Supports TDM, I2S, and similar formats
    • Supports DIT mode
    • Built-In FIFO buffers for optimized system traffic
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and receive clocks up to 50 MHz
    • Two clock zones and two serial-data pins
    • Supports TDM, I2S, and similar formats
  • Real-time control interfaces:
  • Six Enhanced High Resolution Pulse Width Modulation (eHRPWM) Modules, Each Counter supports:
    • Dedicated 16-Bit Time-Base with Period and Frequency Control
    • Two independent PWM outputs with single edge operation
    • Two independent PWM outputs with dual-edge symmetric operation
    • One independent PWM output with dual-edge asymmetric operation
  • Two 32-Bit Enhanced Capture Modules (eCAP):
    • Supports one capture input or one auxiliary PWM output configuration options
    • 4-Event time-stamp registers (Each 32-Bits)
    • Interrupt on either of the four events
  • Three 32-Bit Enhanced Quadrature Pulse Encoder Modules (eQEP), each supports:
    • Quadrature decoding
    • Position counter and control unit for position measurement
    • Unit time base for speed and frequency measurement
  • General connectivity:
  • Two Controller Area Network (CAN) Ports
    • Supports CAN v2.0 Part A, B (ISO 11898-1) protocol
    • Bit rates up to 1 Mbps
    • Dual clock source
    • ECC protection for message RAM
  • One Media Local Bus (MLB)
    • Supports both 3-pin (up to MOST50, 1024 × Fs) and 6-pin (up to MOST150, 2048 × Fs) versions of MediaLB® Physical layer specification v4.2
    • Supports all types of data transfer over 64 logical channels (synchronous stream, isochronous, asynchronous packet, control message)
    • Supports 3-wire MOST 150 protocol
  • Three Inter-Integrated Circuit (I2C) interfaces, each supports:
    • Standard (up to 100 kHz) and
      Fast (up to 400 kHz) modes
    • 7-Bit addressing mode
    • Supports EEPROM size up to 4Mbit
  • Four Serial Peripheral Interfaces (SPI), each supports:
    • Operates at up to 50 MHz in master mode and 25 MHz in slave mode
    • Two chip selects
  • Three UART interfaces
    • All UARTs are 16C750-compatible and operate at up to 3M baud
    • UART0 supports 8 pins with full modem control, with DSR, DTR, DCD, and RI signals
    • UART1 and UART2 are 4-pin interfaces
  • General-Purpose I/O (GPIO)
    • Up to 212 GPIOs muxed with other interfaces
    • Can be configured as interrupt pins
  • Timers and miscellaneous modules:
  • Seven 64-Bit timers:
    • Two 64-Bit timers dedicated to Arm A15 and DSP cores (one timer per core)
      • Watchdog and General-Purpose (GP)
    • Four 64-Bit timers are shared for general purposes
    • Each 64-Bit timer can be configured as two individual 32-Bit timers
    • One 64-Bit timer dedicated for PMMC
    • Two timers input/output pin pairs
  • Interprocessor communication with:
    • Message manager to facilitate multiprocessor access to the PMMC:
      • Provides hardware acceleration for pushing and popping messages to/from logical queues
      • Supports up to 64 queues and 128 messages
    • Semaphore module with up to 64 independent semaphores and 16 masters (device cores)
  • EDMA with 128 (2 × 64) channels and
    1024 (2 × 512) PaRAM entries
  • Keystone II System on Chip (SoC) architecture:
  • Security
    • Supports General-Purpose (GP) and High-Secure (HS) devices
    • Supports secure boot
    • Supports customer secondary keys
    • 4KB of One-Time Programmable (OTP) ROM for customer keys
  • Power management
    • Integrated Power Management Microcontroller (PMMC) technology
  • Supports primary boot from UART, I2C, SPI, GPMC, SD or eMMC, USB device firmware upgrade v1.1, PCIe®, and Ethernet interfaces
  • Keystone II debug architecture with integrated Arm CoreSight™ support and trace capability
  • Operating Temperature (TJ):
  • –40°C to 125°C (Industrial Extended)
  • –40°C to 105°C (Extended)
  • 0°C to 90°C (Commercial)

66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.

Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.

66AK2G1x is a family of heterogeneous multicore System-on-Chip (SoC) devices based on TI’s field-proven Keystone II (KS2) architecture. These devices address applications that require both DSP and Arm performance, with integration of high-speed peripheral and memory interfaces, hardware acceleration for network and cryptography functions, and high-level operating systems (HLOS) support.

Similar to existing KS2-based SoC devices, the 66AK2G1x enables both the DSP and Arm cores to master all memory and peripherals in the system. This architecture facilitates maximum software flexibility where either DSP- or Arm-centric system designs can be achieved.

The 66AK2G1x significantly improves device reliability by extensively implementing error correction code (ECC) in processor cores, shared memory, embedded memory in modules, and external memory interfaces. Full analysis of soft error rate (SER) and power-on-hours (POH) shows that the designated 66AK2G1x parts satisfy a wide range of industrial requirements.

Accompanied by the new Processor SDK, the 66AK2G1x development platform enables unprecedented ease-of-use with main line open source Linux, Code Composer Studio™ (CCS) - Integrated Development Environment (IDE), a wide range of OS-independent device drivers, as well as TI-RTOS that enables seamless task management across processor cores. The device also features advanced debug and trace technology with the latest innovations from TI and Arm, such as system trace and seamless integration of the Arm CoreSight components.

Secure boot can also be made available for anticloning and illegal software update protection. For more information about secure boot, contact your TI sales representative.
filter 기타 오디오 및 레이더 DSP SoC 찾기
다운로드 스크립트와 함께 비디오 보기 비디오
TI에서 제공하는 제한된 설계 지원

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기술 자료

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42개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 66AK2G1x Multicore DSP+Arm KeyStone II System-on-Chip (SoC) datasheet (Rev. F) PDF | HTML 2019. 12. 10
* 사용 설명서 66AK2Gx Multicore DSP + ARM Keystone II System-on-Chip (SOC) TRM (Rev. I) 2019. 2. 25
* 사용 설명서 K2G General Purpose Evaluation Module (EVMK2G) TRM (Rev. A) 2017. 9. 20
* 정오표 66AK2G1x Errata (Rev. B) 2018. 6. 20
애플리케이션 노트 Industrial Communication Protocols Supported on TI Processors and MCUs (Rev. F) PDF | HTML 2025. 9. 3
애플리케이션 노트 High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023. 2. 24
애플리케이션 노트 PRU-ICSS Feature Comparison (Rev. G) PDF | HTML 2022. 10. 11
애플리케이션 노트 DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022. 7. 7
애플리케이션 노트 Keystone Error Detection and Correction EDC ECC (Rev. A) 2021. 6. 25
애플리케이션 노트 How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021. 5. 19
애플리케이션 노트 Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019. 6. 11
애플리케이션 노트 KeyStone II DDR3 interface bring-up PDF | HTML 2019. 3. 7
백서 Designing professional audio mixers for every scenario 2018. 6. 28
설계 가이드 DDR ECC Reference Design to Improve Memory Reliability in 66AK2Gx-Based Systems (Rev. B) 2018. 6. 12
애플리케이션 노트 66AK2G1x: EVMK2GX General-Purpose EVM Power Distribution Network Analysis 2018. 3. 14
사용 설명서 PRU Assembly Instruction User Guide 2018. 2. 16
애플리케이션 노트 66AK2G12 Power Consumption Summary 2018. 2. 9
애플리케이션 노트 66AK2G12 Power Estimation Tool 2018. 1. 19
사용 설명서 TPS65911A User’s Guide for 66AK2G12 Processor (Rev. A) 2017. 12. 18
사용 설명서 66AK2Gx BGA Escape Routing Stackup (Rev. A) 2017. 11. 14
사용 설명서 66AK2Gx Hardware Design Guide (Rev. A) 2017. 11. 14
애플리케이션 노트 66AK2Gx Schematic Checklist (Rev. A) 2017. 11. 14
백서 Designing Embedded Systems for High Reliability With 66AK2Gx (Rev. A) 2017. 8. 28
백서 Getting personal with the 66AK2Gx SoC (Rev. A) 2017. 8. 2
추가 자료 K2G General-Purpose (GP) EVM Quick Start Guide (Rev. A) 2017. 7. 27
백서 Voice as the user interface – a new era in speech processing white Paper 2017. 5. 9
애플리케이션 노트 Processor SDK RTOS Audio Benchmark Starter Kit 2017. 4. 12
사용 설명서 K2G Industrial Communications Engine (K2G ICE) 2017. 2. 28
추가 자료 K2G Industrial Communications Engine (ICE) Quick Start Guide 2017. 2. 2
사용 설명서 TPS659118 User’s Guide for 66AK2G02 Processor 2016. 5. 2
애플리케이션 노트 SERDES Link Commissioning on KeyStone I and II Devices 2016. 4. 13
추가 자료 K2G Audio Daughter Card Quick Start Guide 2016. 3. 14
백서 Multicore SoCs stay a step ahead of SoC FPGAs 2016. 2. 23
애플리케이션 노트 TI DSP Benchmarking PDF | HTML 2016. 1. 13
애플리케이션 노트 Keystone II DDR3 Debug Guide 2015. 10. 16
애플리케이션 노트 Keystone II DDR3 Initialization 2015. 1. 26
애플리케이션 노트 Hardware Design Guide for KeyStone II Devices 2014. 3. 24
사용 설명서 C66x CorePac User's Guide (Rev. C) 2013. 6. 28
애플리케이션 노트 Introduction to TMS320C6000 DSP Optimization 2011. 10. 6
백서 Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011. 5. 19
사용 설명서 C66x CPU and Instruction Set Reference Guide 2010. 11. 9
사용 설명서 C66x DSP Cache User's Guide 2010. 11. 9

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

개발 키트

EVMK2GX — 66AK2Gx 1GHz 평가 모듈

EVMK2GX("K2G"라고도 함) 1GHz EVM(평가 모듈)을 사용하면 개발자가 66AK2Gx 프로세서 제품군의 평가를 즉시 시작하고 오디오, 산업용 모터 제어, 스마트 그리드 보호 및 기타 고신뢰성, 실시간 컴퓨팅 집약적 애플리케이션의 개발을 가속화할 수 있습니다. 기존의 KeyStone 기반 SoC 장치와 마찬가지로 66AK2Gx는 DSP 및 Arm® 코어가 모두 시스템의 모든 메모리와 주변 장치를 마스터할 수 있습니다. 이 아키텍처는 DSP 중심 또는 Arm 중심의 시스템 설계를 달성할 수 있는 소프트웨어 유연성을 (...)

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제한:
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이용할 수 없음
도터 카드

AUDK2G — 66AK2Gx(K2G) 오디오 부속 카드

K2G 오디오 부속 카드는 K2G 범용 EVM(EVMK2G) 또는 EVMK2GX와 함께 작동하도록 설계되었으며 EVMK2G 또는 EVMK2GX는 오디오 부속 카드 작동에 필요합니다.  부속 카드를 사용하면 66AKG2G02 DSP + ARM® 프로세서 SoC를 기반으로 A/V 리시버, 사운드바, 차량용 증폭기 시스템 및 믹싱 콘솔과 같은 멀티 채널 오디오 애플리케이션을 개발할 수 있습니다.

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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-K2G — Linux Processor SDK for K2Gx

프로세서 SDK(소프트웨어 개발 키트)는 TI 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로, 이를 통해 벤치마크와 데모를 손쉽게 설정하고 빠르고 간편하게 액세스할 수 있습니다. 프로세서 SDK의 모든 릴리스는 TI의 광범위한 포트폴리오 내에서 일관되므로 개발자는 디바이스간에 소프트웨어를 자유롭게 재사용하고 마이그레이션할 수 있습니다. 프로세서 SDK와 TI의 임베디드 프로세서 솔루션을 사용하면 그 어느 때보다 쉽게 확장 가능한 플랫폼 솔루션을 개발할 수 있습니다.

프로세서 SDK에는 Linux 및 TI-RTOS 운영 체제 (...)

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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-LINUX-RT-K2G — Linux-RT Processor SDK for K2G

프로세서 SDK(소프트웨어 개발 키트)는 TI 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로, 이를 통해 벤치마크와 데모를 손쉽게 설정하고 빠르고 간편하게 액세스할 수 있습니다. 프로세서 SDK의 모든 릴리스는 TI의 광범위한 포트폴리오 내에서 일관되므로 개발자는 디바이스간에 소프트웨어를 자유롭게 재사용하고 마이그레이션할 수 있습니다. 프로세서 SDK와 TI의 임베디드 프로세서 솔루션을 사용하면 그 어느 때보다 쉽게 확장 가능한 플랫폼 솔루션을 개발할 수 있습니다.

프로세서 SDK에는 Linux 및 TI-RTOS 운영 체제 (...)

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소프트웨어 개발 키트(SDK)

PROCESSOR-SDK-RTOS-K2G — TI-RTOS Processor SDK for K2Gx (No design support from TI available. Refer to Overview- RTOS Highlights for details.)

프로세서 SDK(소프트웨어 개발 키트)는 TI 임베디드 프로세서를 위한 통합 소프트웨어 플랫폼으로, 이를 통해 벤치마크와 데모를 손쉽게 설정하고 빠르고 간편하게 액세스할 수 있습니다. 프로세서 SDK의 모든 릴리스는 TI의 광범위한 포트폴리오 내에서 일관되므로 개발자는 디바이스간에 소프트웨어를 자유롭게 재사용하고 마이그레이션할 수 있습니다. 프로세서 SDK와 TI의 임베디드 프로세서 솔루션을 사용하면 그 어느 때보다 쉽게 확장 가능한 플랫폼 솔루션을 개발할 수 있습니다.

프로세서 SDK에는 Linux 및 TI-RTOS 운영 체제 (...)

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IDE, 구성, 컴파일러 또는 디버거

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

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드라이버 또는 라이브러리

AEC-AER — Acoustic echo cancellation/removal for TI C64x+, C674x, C55x and Cortex®-A8 processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

FAXLIB — FAX library (FAXLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

지원되는 제품 및 하드웨어
드라이버 또는 라이브러리

PRU-ICSS-INDUSTRIAL-SW — Sitara™ 프로세서용 PRU-ICSS 산업용 소프트웨어

PRU-ICSS 프로토콜은 TI Sitara 프로세서를 위한 실시간 산업용 통신을 지원합니다.  PRU-ICSS 프로토콜은 TI의 통합 소프트웨어 개발 플랫폼인 Processor-SDK-RTOS를 기반으로 사용하도록 구축되었으며 최적화된 PRU-ICSS 펌웨어, ARM 프로세서에 해당하는 PRU-ICSS 드라이버 및 예제 애플리케이션을 포함하고 있습니다. PRU-ICSS 펌웨어는 PRU 코어에서 실행되며 기본 ARM 프로세서에서 시간이 중요한 링크 계층 프로세싱을 오프로드하고 TI-RTOS를 실행합니다. PRU-ICSS 드라이버는 (...)

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드라이버 또는 라이브러리

VOLIB — Voice library (VoLIB) for C66x, C64x+ and C55x processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

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소프트웨어 코덱

AURO-3P-3DENGINE — Auro Technologies Auro-CODEC 및 Auro-Matic 소프트웨어

Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.
발송: Auro Technologies N.V.
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시뮬레이션 모델

66AK2G12 BSDL Model

SPRM715.ZIP (24 KB) - BSDL 모델
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시뮬레이션 모델

66AK2G12 IBIS Model

SPRM705.ZIP (1918 KB) - IBIS 모델
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시뮬레이션 모델

66AK2G12 Thermal Model

SPRM716.ZIP (3 KB) - 열 모델
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시뮬레이션 모델

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI 모델
lock = 수출 승인 필요(1분)
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계산 툴

CLOCKTREETOOL — Sitara, 오토모티브, 비전 분석 및 디지털 신호 프로세서용 클록 트리 툴

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
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레퍼런스 디자인

TIDEP-0088 — 음성 기반 애플리케이션을 위한 오디오 전처리 시스템 레퍼런스 디자인

이 레퍼런스 설계는 다중 마이크, 빔포밍 알고리즘 및 기타 프로세스를 사용하여 잡음 및 기타 혼잡한 환경에서 선명한 음성 및 오디오를 추출합니다.  잡음이 잦은 음성 인식 디지털 어시스턴트용 환경에서 사용되는 애플리케이션의 급속한 증가로 인해 잡음이 많은 환경에서 선명한 음성을 추출하는 시스템에 대한 수요가 생겼습니다.  이 레퍼런스 설계는 마이크 어레이와 정교한 신호 처리를 사용해 잡음이 심한 환경에서 선명한 오디오를 추출합니다.
지원되는 제품 및 하드웨어
레퍼런스 디자인

TIDEP0067 — 66AK2Gx DSP + ARM 프로세서 전원 솔루션 레퍼런스 디자인

이 레퍼런스 설계는 66AK2Gx 멀티코어 시스템 온 칩(SoC) 프로세서와 66AK2Gx 프로세서를 위한 전원 공급 장치 및 전원 시퀀싱을 단일 장치에 포함하는 컴패니언 TPS65911 전력 관리 통합 회로(PMIC)를 기반으로 합니다. 이 전원 솔루션 설계에는 12V 입력을 지원하는 1단계 벅 컨버터와 DDR3L 메모리용 DDR 종단 레귤레이터도 포함되어 있습니다. 레퍼런스 설계는 테스트를 거쳤으며 하드웨어 레퍼런스(EVM), 소프트웨어(프로세서 SDK) 및 테스트 데이터가 포함되어 있습니다.
지원되는 제품 및 하드웨어
레퍼런스 디자인

TIDEP0068 — K2G 범용 EVM(GP EVM)을 위한 PCI Express PCB 설계 고려 사항 레퍼런스 디자인

PCI-Express는 방향에 따라 레인당 최대 5.0Gbps 속도의 데이터 전송을 통해 적은 핀 수, 높은 안정성 및 높은 속도를 제공하며, PCIe 모듈은 TI 66AK2Gx DSP + ARM 프로세서 SoC(시스템 온 칩)에 포함되어 있습니다.  이 PCIe PCB 설계 고려 사항 레퍼런스 설계는 66AK2Gx 프로세서 SoC의 PCIe 부분에 대한 모범 사례 PCB를 제공하여 개발자가 PCB(인쇄 회로 보드) 설계를 최적화하는 데 도움이 됩니다.  이를 통해 개발자는 첫 번째 PCB 구현 패스에서 원하는 PCIe 신호 (...)

지원되는 제품 및 하드웨어
레퍼런스 디자인

TIDEP0069 — 66AK2Gx DSP + ARM 프로세서 오디오 프로세싱 레퍼런스 디자인

이 레퍼런스 설계는 66AK2Gx DSP + ARM 프로세서 시스템 온 칩(SoC)과 컴패니언 AIC3106 오디오 코덱을 기반으로 하는 레퍼런스 플랫폼이며 오디오 처리 알고리즘 설계 및 데모를 빠르게 진행할 수 있는 경로를 제공합니다. 이 오디오 솔루션 설계에는 DSP에서 오디오 효과를 추가하기 위한 오디오 처리 블록을 보여주는 프로세서 SDK TI RTOS 소프트웨어를 사용하는 실시간 애플리케이션 소프트웨어가 포함되어 있습니다. 
지원되는 제품 및 하드웨어
레퍼런스 디자인

TIDEP0070 — 66AK2Gx 기반 시스템의 메모리 안정성 향상을 위한 DDR ECC 레퍼런스 디자인

이 레퍼런스 설계는 66AK2Gx 멀티코어 DSP + ARM 프로세서 SoC(시스템 온 칩) 기반의 고신뢰성 애플리케이션에서 ECC(오류 정정 코드)를 지원하는 DDR(듀얼 데이터 레이트) 메모리 인터페이스에 대한 시스템 고려 사항을 설명합니다.  개발자는 시스템 인터페이스, 보드 하드웨어, 소프트웨어, 처리량 성능 및 진단 절차를 논의함으로써 고신뢰성 기반 솔루션을 신속하게 구현할 수 있습니다.
지원되는 제품 및 하드웨어
패키지 핀 CAD 기호, 풋프린트 및 3D 모델
FCCSP (ABY) 625 Ultra Librarian
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