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TXG4020

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2-Bit-Umsetzer mit fester Richtung und ±40 V Masseverschiebung, 2/0-Konfiguration

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TXG4020

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Produktdetails

Rating Catalog Ground offset voltage (max) (V) 40 Bits (#) 2 Topology Push-Pull Applications GPIO Forward/reverse channels 2 forward / 0 reverse Isolation rating Functional Data rate (max) (Mbps) 250 Prop delay (ns) 5.9 CMTI (V/µs) 1000 Technology family TXG Vin (min) (V) 1.71 Vin (max) (V) 5.5 Vout (min) (V) 1.71 Vout (max) (V) 5.5 Current consumption per channel (1 Mbps) (typ) (mA) 3.3 Features Partial power down (Ioff)
Rating Catalog Ground offset voltage (max) (V) 40 Bits (#) 2 Topology Push-Pull Applications GPIO Forward/reverse channels 2 forward / 0 reverse Isolation rating Functional Data rate (max) (Mbps) 250 Prop delay (ns) 5.9 CMTI (V/µs) 1000 Technology family TXG Vin (min) (V) 1.71 Vin (max) (V) 5.5 Vout (min) (V) 1.71 Vout (max) (V) 5.5 Current consumption per channel (1 Mbps) (typ) (mA) 3.3 Features Partial power down (Ioff)
WSON (DSG) 8 4 mm² (2 mm × 2 mm) SOIC (D) 8 29.4 mm² (4.9 mm × 6 mm) SOT-23-THN (DDF) 8 8.12 mm² (2.9 mm × 2.8 mm)
  • Supports DC shifts up to ±40V
  • AC Noise Rejection of 80VPP up to 5MHz
  • CMTI of 1kV/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (<0.20ns)
  • Greater than 250Mbps
  • Low power consumption (0.8mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • 4, 2, 1 channel devices with multiple configurations will be available
  • Two device variants:
    • TXG4020: 2 forward
    • TXG4021: 1 forward, 1 reverse
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
    • ESD protection exceeds JESD 22
    • 2500V human-body model
    • 500V charged-device model
  • Package options provided:
    • DSG (WSON-8)
    • DDF (SOT-8)
    • D (SOIC-8)
  • Supports DC shifts up to ±40V
  • AC Noise Rejection of 80VPP up to 5MHz
  • CMTI of 1kV/µs
  • Low Prop Delay (<5ns) and Ch-Ch Skew (<0.20ns)
  • Greater than 250Mbps
  • Low power consumption (0.8mA per channel at 1Mbps, 1.8V)
  • Fully configurable dual-rail design allows each port to operate from 1.71V to 5.5V
  • 4, 2, 1 channel devices with multiple configurations will be available
  • Two device variants:
    • TXG4020: 2 forward
    • TXG4021: 1 forward, 1 reverse
  • Supports VCC disconnect feature (I/Os are forced into high-Z)
  • Schmitt-trigger inputs allows for slow and noisy signals
  • Inputs with integrated static pull-down resistors prevent channels from floating
  • Operating temperature from –40°C to +125°C
  • Latch-up performance exceeds 100mA per JESD 78, class II
    • ESD protection exceeds JESD 22
    • 2500V human-body model
    • 500V charged-device model
  • Package options provided:
    • DSG (WSON-8)
    • DDF (SOT-8)
    • D (SOIC-8)

The TXG402x is a 2-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXG402x family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. The leakage between GNDA and GNDB is <90nA when VCC to GND is shorted.

The TXG402x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 80VPP up to 5MHz (Figure 7-5). This device can support multiple interfaces such as UART, GPIO, and JTAG.

The TXG402x is a 2-bit, fixed direction, non-galvanic based voltage and ground-level translator that can support both logic-level shifting between 1.71V to 5.5V and ground-level shifting up to ±40V. Compared to traditional level shifters, the TXG402x family can solve the challenges of voltage translation across different ground levels. The Simplified Diagram shows a common use case where DC shift occurs between GNDA to GNDB due to parasitic resistance or capacitance.

VCCA is referenced to GNDA and VCCB is referenced to GNDB. Ax pins are referenced to VCCA logic level while Bx pins are referenced to VCCB logic levels. Both A port and B port can accept voltages from 1.71V to 5.5V. The leakage between GNDA and GNDB is <90nA when VCC to GND is shorted.

The TXG402x device helps improve noise immunity and power sequencing across different ground domains while providing low power consumption, latency and channel-to-channel skew. It can supress noise levels of 80VPP up to 5MHz (Figure 7-5). This device can support multiple interfaces such as UART, GPIO, and JTAG.
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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt TXG402x 2-bit , ± 40V Ground-Level Translator datasheet (Rev. A) PDF | HTML 25.07.2025
Application brief Solving Ground Shift Issues in Phase Array Satellites PDF | HTML 30.07.2026
Application brief Top Questions about Ground-Level Translators PDF | HTML 27.05.2026
Technischer Artikel Uneven grounds? Address offset challenges with novel ground-level translators (Rev. A) PDF | HTML 05.06.2025
Application brief Not All Grounds Are 0V PDF | HTML 21.05.2025
Product overview TI's Latest Ground-Level Translators PDF | HTML 07.05.2025

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