Produktdetails

Number of ADC channels 2 Number of DAC channels 2 Digital audio interface I2S, LJ, TDM Control interface I2C, SPI Analog inputs 2 Analog outputs 2, 4 Features Digital mic support, Fault Diagnostic, Headset detect, Low latency, Low power, Matrix mixing, Mic bias, Phase-locked loop (PLL), Single supply, Stereo headphone amplifier, Thermal Foldback Sampling rate (max) (kHz) 768 Rating Automotive ADC SNR (typ) (dB) 104 DAC SNR (typ) (dB) 114 Operating temperature range (°C) -40 to 125
Number of ADC channels 2 Number of DAC channels 2 Digital audio interface I2S, LJ, TDM Control interface I2C, SPI Analog inputs 2 Analog outputs 2, 4 Features Digital mic support, Fault Diagnostic, Headset detect, Low latency, Low power, Matrix mixing, Mic bias, Phase-locked loop (PLL), Single supply, Stereo headphone amplifier, Thermal Foldback Sampling rate (max) (kHz) 768 Rating Automotive ADC SNR (typ) (dB) 104 DAC SNR (typ) (dB) 114 Operating temperature range (°C) -40 to 125
WQFN (RTV) 32 25 mm² 5 x 5
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ +125°C
  • Stereo audio ADC channel
    • Performance:
      • Line/Microphone differential input dynamic range: 104dB
      • Differential input THD+N: –97dB
      • Channel summing mode supports high SNR: 107dB
    • Input voltage:
      • Differential, 10VRMS full-scale inputs
      • Single-ended, 5VRMS full-scale inputs
    • ADC sample rate (fS) = 4kHz to 768kHz
    • Programmable microphone bias (3V to 10V):
      • With an integrated efficient boost converter, or
      • With external high voltage HVDD supply
    • Programmable microphone input fault diagnostics:
      • Open inputs or shorted inputs
      • Short to ground, MICBIAS or VBAT
      • Microphone bias over current protection
  • Stereo audio DAC channel
    • Performance:
      • DAC to differential line-out dynamic range: 114dB
      • DAC to single-ended headphone-out dynamic range: 107dB
      • Differential output THD+N: –96dB
    • Line-out/Headphone output voltage:
      • Differential, 2VRMS full-scale
      • Single-ended, 1VRMS full-scale
    • DAC sample rate (fs) = 4kHz to 768kHz
  • Common Features
    • Low-latency and Ultra low-latency decimation/interpolation filter options
    • Programmable HPF and biquad digital filters
    • I2C or SPI control interface
    • Audio Serial Interface
      • Format: TDM, I2S or Left-justified (LJ)
      • Word Length: 16, 20, 24 or 32 Bits
    • Programmable PLL for flexible clocking
    • Low Power Modes
    • Single supply operation AVDD: 3.3V
    • I/O supply operation: 1.2V or 1.8V or 3.3V
  • AEC-Q100 qualified for automotive applications
    • Temperature grade 1: –40°C ≤ TA ≤ +125°C
  • Stereo audio ADC channel
    • Performance:
      • Line/Microphone differential input dynamic range: 104dB
      • Differential input THD+N: –97dB
      • Channel summing mode supports high SNR: 107dB
    • Input voltage:
      • Differential, 10VRMS full-scale inputs
      • Single-ended, 5VRMS full-scale inputs
    • ADC sample rate (fS) = 4kHz to 768kHz
    • Programmable microphone bias (3V to 10V):
      • With an integrated efficient boost converter, or
      • With external high voltage HVDD supply
    • Programmable microphone input fault diagnostics:
      • Open inputs or shorted inputs
      • Short to ground, MICBIAS or VBAT
      • Microphone bias over current protection
  • Stereo audio DAC channel
    • Performance:
      • DAC to differential line-out dynamic range: 114dB
      • DAC to single-ended headphone-out dynamic range: 107dB
      • Differential output THD+N: –96dB
    • Line-out/Headphone output voltage:
      • Differential, 2VRMS full-scale
      • Single-ended, 1VRMS full-scale
    • DAC sample rate (fs) = 4kHz to 768kHz
  • Common Features
    • Low-latency and Ultra low-latency decimation/interpolation filter options
    • Programmable HPF and biquad digital filters
    • I2C or SPI control interface
    • Audio Serial Interface
      • Format: TDM, I2S or Left-justified (LJ)
      • Word Length: 16, 20, 24 or 32 Bits
    • Programmable PLL for flexible clocking
    • Low Power Modes
    • Single supply operation AVDD: 3.3V
    • I/O supply operation: 1.2V or 1.8V or 3.3V

The TAC5312-Q1 is a low-power stereo audio codec with 10VRMS differential input, 104dB ADC and 2VRMS differential output, 114dB DAC. The TAC5312-Q1 supports both differential and single-ended inputs and outputs. The device supports both microphone and line inputs on the ADC channels with options for AC and DC coupling configurations. The DAC outputs can be configured for either line-out or headphone loads. TAC5312-Q1 can drive up to 62.5mW into a 16Ω headphone load. The device also offers an integrated high-voltage, programmable microphone bias and input diagnostic circuitry that allows direct connection to microphone-based automotive systems with complete fault diagnostic capability for direct-coupled inputs. The TAC5312-Q1 integrates an efficient boost converter to generate a high-voltage microphone bias using an external, low-voltage, 3.3V supply. The device can also directly use an external high-voltage supply (HVDD), which is any readily available supply in the system to generate this microphone bias. The TAC5312-Q1 integrates a programmable channel gain, digital volume control, a low-jitter phase-locked loop (PLL), a programmable high-pass filter (HPF), programmable EQ and biquad filters, and interpolation and decimation filters with low and ultra-low latency filter modes. The device allows for sample rates up to 768kHz. The TAC5312-Q1 supports time-division multiplexing (TDM), I2S, or left-justified (LJ) audio formats and can be controlled with I2C or SPI. These integrated high-performance features, along with a single, 3.3V supply operation, make TAC5312-Q1 an excellent choice for space-constrained automotive systems.

The TAC5312-Q1 is a low-power stereo audio codec with 10VRMS differential input, 104dB ADC and 2VRMS differential output, 114dB DAC. The TAC5312-Q1 supports both differential and single-ended inputs and outputs. The device supports both microphone and line inputs on the ADC channels with options for AC and DC coupling configurations. The DAC outputs can be configured for either line-out or headphone loads. TAC5312-Q1 can drive up to 62.5mW into a 16Ω headphone load. The device also offers an integrated high-voltage, programmable microphone bias and input diagnostic circuitry that allows direct connection to microphone-based automotive systems with complete fault diagnostic capability for direct-coupled inputs. The TAC5312-Q1 integrates an efficient boost converter to generate a high-voltage microphone bias using an external, low-voltage, 3.3V supply. The device can also directly use an external high-voltage supply (HVDD), which is any readily available supply in the system to generate this microphone bias. The TAC5312-Q1 integrates a programmable channel gain, digital volume control, a low-jitter phase-locked loop (PLL), a programmable high-pass filter (HPF), programmable EQ and biquad filters, and interpolation and decimation filters with low and ultra-low latency filter modes. The device allows for sample rates up to 768kHz. The TAC5312-Q1 supports time-division multiplexing (TDM), I2S, or left-justified (LJ) audio formats and can be controlled with I2C or SPI. These integrated high-performance features, along with a single, 3.3V supply operation, make TAC5312-Q1 an excellent choice for space-constrained automotive systems.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet TAC5312-Q1 Automotive Stereo Audio Codec with 104 dB ADC, 110 dB DAC, High-Voltage Input, Micbias and Diagnostics datasheet (Rev. A) PDF | HTML 10 Mär 2025
Application note Using the TAC5x1x-Q1 Audio Codec in Automotive Infotainment Systems PDF | HTML 26 Feb 2026
Product overview Four Considerations for Designing Emergency Call (eCall) PDF | HTML 02 Feb 2026
Application brief TAC5x1x and TAC5x1x-Q1 Programmable Biquad Filters - Configuration and Applications PDF | HTML 27 Sep 2024
Application note Clocking Configuration of Device and Flexible Clocking For TAx5x1x Family (Rev. A) PDF | HTML 05 Sep 2024
Application note Inter Chip Limiter Alignment in TAx5xxx-Q1 Devices PDF | HTML 29 Aug 2024
Application note Dynamic Voltage and Temperature Tracking Based Limiter in TAX5XXX-Q1 PDF | HTML 20 Aug 2024
Application note TAx5xxx-Q1 Fault Diagnostic Features PDF | HTML 15 Nov 2023
Application note Clock Error Configuration, Detection, and Modes Supported in TAx5x1x Family PDF | HTML 07 Nov 2023
Application note Analog Input Configurations, Mixing and Muxing of TAx5x1x-Q1 Devices PDF | HTML 30 Okt 2023

Design und Entwicklung

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Download-Optionen
Support-Software

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Referenzdesigns

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