SN74LVTH245A

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Achtfach-ABT-Bustransceiver, 3,3 V, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN54LVTH245A, SN74LVTH245A datasheet (Rev. T) (Englisch)

SN74LVTH245A

AKTIV

Datenblatt

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Produktdetails

Number of channels

8

IOL (max) (mA)

64

IOH (max) (mA)

-64

Input type

TTL/CMOS

Output type

LVTTL

Features

Balanced outputs

Technology family

LVT

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Number of channels

8

IOL (max) (mA)

64

IOH (max) (mA)

-64

Input type

TTL/CMOS

Output type

LVTTL

Features

Balanced outputs

Technology family

LVT

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SOP (NS)

20

98.28 mm² (12.6 mm × 7.8 mm)

VQFN (RGY)

20

15.75 mm² (4.5 mm × 3.5 mm)

SSOP (DB)

20

56.16 mm² (7.2 mm × 7.8 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
I_off and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Support Unregulated Battery Operation Down to 2.7 V
I_off and Power-Up 3-State Support Hot Insertion
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 500 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

These octal bus transceivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

These devices are designed for asynchronous communication between data buses. They transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the devices so the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These octal bus transceivers are designed specifically for low-voltage (3.3-V) V_CC operation, but with the capability to provide a TTL interface to a 5-V system environment.

These devices are designed for asynchronous communication between data buses. They transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the devices so the buses are effectively isolated.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

These devices are fully specified for hot-insertion applications using I_off and power-up 3-state. The I_off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

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Technische Dokumentation

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Alle anzeigen 3

Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	SN54LVTH245A, SN74LVTH245A datasheet (Rev. T)		11.09.2003
	Auswahlhilfe	Logic Guide (Rev. AC)	PDF \| HTML	13.11.2025
	Anwendungshinweis	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		17.09.2018

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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