SN74LVC4245A

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Achtfach-Bustransceiver und Umsetzer von 3,3 auf 5 V, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74LVC4245A Octal Bus Transceiver and 3.3V to 5V Shifter With 3-State Outputs datasheet (Rev. K) (Englisch) PDF | HTML

SN74LVC4245A

AKTIV

Jetzt bestellen

Produktdetails

Bits (#)

8

Data rate (max) (Mbps)

200

Topology

Push-Pull

Vin (min) (V)

4.5

Vin (max) (V)

5.5

Vout (min) (V)

2.7

Vout (max) (V)

5.5

Applications

GPIO, JTAG, SPI, UART

Features

Output enable

Prop delay (ns)

6.7

Technology family

LVC

Supply current (max) (mA)

0.13

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Bits (#)

8

Data rate (max) (Mbps)

200

Topology

Push-Pull

Vin (min) (V)

4.5

Vin (max) (V)

5.5

Vout (min) (V)

2.7

Vout (max) (V)

5.5

Applications

GPIO, JTAG, SPI, UART

Features

Output enable

Prop delay (ns)

6.7

Technology family

LVC

Supply current (max) (mA)

0.13

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DB)

24

63.96 mm² (8.2 mm × 7.8 mm)

SOIC (DW)

24

159.65 mm² (15.5 mm × 10.3 mm)

TSSOP (PW)

24

49.92 mm² (7.8 mm × 6.4 mm)

8-bit direction controlled translating bus transceiver
5.5V on A port and 2.7V to 3.6V on B port
High drive strength for heavier loading conditions
- 24mA at 3V supply
Robust, glitch-free power supply sequencing
VCC isolation and VCC disconnect feature
- If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
Control inputs VIH/VIL levels are referenced to VCCA voltage
Ioff supports Partial-Power-Down node operation
Latch-up performance exceeds 250mA per JESD 17
Operating temperature range -40°C to 85°C
ESD protection exceeds JESD 22
- 2000V Human-Body Model
- 1000V Charged-Device Model
Compatible with SN74LVC4245

8-bit direction controlled translating bus transceiver
5.5V on A port and 2.7V to 3.6V on B port
High drive strength for heavier loading conditions
- 24mA at 3V supply
Robust, glitch-free power supply sequencing
VCC isolation and VCC disconnect feature
- If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
Control inputs VIH/VIL levels are referenced to VCCA voltage
Ioff supports Partial-Power-Down node operation
Latch-up performance exceeds 250mA per JESD 17
Operating temperature range -40°C to 85°C
ESD protection exceeds JESD 22
- 2000V Human-Body Model
- 1000V Charged-Device Model
Compatible with SN74LVC4245

This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set at 3.3V, and A port has VCCA, which is set at 5V. This allows for translation from a 3.3V to a 5V environment, and vice versa.

The SN74LVC4245A device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.

The SN74LVC4245A device terminal out allows the designer to switch to a normal all 3.3V or all 5V 20-terminal SN74LVC4245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A device to align with the conventional ’245 terminal out.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling the outputs.

This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set at 3.3V, and A port has VCCA, which is set at 5V. This allows for translation from a 3.3V to a 5V environment, and vice versa.

The SN74LVC4245A device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.

The SN74LVC4245A device terminal out allows the designer to switch to a normal all 3.3V or all 5V 20-terminal SN74LVC4245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A device to align with the conventional ’245 terminal out.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling the outputs.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen
*	Datenblatt	SN74LVC4245A Octal Bus Transceiver and 3.3V to 5V Shifter With 3-State Outputs datasheet (Rev. K)	PDF \| HTML	29.05.2026
	Anwendungshinweis	Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators	PDF \| HTML	02.10.2024
	Anwendungshinweis	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	12.07.2024
	Anwendungshinweis	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	03.07.2024
	Auswahlhilfe	Voltage Translation Buying Guide (Rev. A)		15.04.2021

Design und Entwicklung

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