SN74LVC2G32

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OR-Gatter, zwei Kanäle, zwei Eingänge 1,65 V bis 5,5 V, 32 mA Treiberstärke

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Datenblatt

document-pdfAcrobat SN74LVC2G32 Dual 2-Input Positive-OR Gate datasheet (Rev. N) (Englisch) PDF | HTML

SN74LVC2G32

AKTIV

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Produktdetails

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

2

Inputs per channel

2

IOL (max) (mA)

32

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns)

Data rate (max) (Mbps)

100

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

DSBGA (YZP)

8

2.8125 mm² (— mm × — mm)

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

Available in the Texas Instruments
NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Maximum t_pd of 3.8 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the V_CC
Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

Available in the Texas Instruments
NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Maximum t_pd of 3.8 ns at 3.3 V
Low Power Consumption, 10-µA Maximum I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce)
<0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output V_OH Undershoot)
>2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the V_CC
Level
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114-A)
- 1000-V Charged-Device Model (C101)

This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G32 device performs the Boolean function Y = A + B or Y = A • B in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V V_CC operation.

The SN74LVC2G32 device performs the Boolean function Y = A + B or Y = A • B in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen		Datum
*	Datenblatt	SN74LVC2G32 Dual 2-Input Positive-OR Gate datasheet (Rev. N)	PDF \| HTML		18.09.2015
	Application brief	Optimizing Board Space for Discrete LOGIC Designs Using Smallest Package Solutio (Rev. A)	PDF \| HTML		29.09.2022

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