SN74LVC2G126

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2-Kanal-Puffer, 1,65 bis 5,5 V mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74LVC2G126 Dual Bus Buffer Gate With 3-State Outputs datasheet (Rev. N) (Englisch) PDF | HTML

SN74LVC2G126

AKTIV

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Produktdetails

Technology family

LVC

Number of channels

2

IOL (max) (mA)

32

Supply current (max) (µA)

10

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LVC

Number of channels

2

IOL (max) (mA)

32

Supply current (max) (µA)

10

IOH (max) (mA)

-32

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

DSBGA (YZP)

8

2.8125 mm² (— mm × — mm)

VSSOP (DCU)

8

6.2 mm² (2 mm × 3.1 mm)

SSOP (DCT)

8

11.8 mm² (2.95 mm × 4 mm)

Available in the Texas Instruments NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4ns at 3.3V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output VOH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model
- 1000-V Charged-Device Model

Available in the Texas Instruments NanoFree™ Package
Supports 5-V V_CC Operation
Inputs Accept Voltages to 5.5 V
Max t_pd of 4ns at 3.3V
Low Power Consumption, 10-µA Max I_CC
±24-mA Output Drive at 3.3 V
Typical V_OLP (Output Ground Bounce) < 0.8 V at V_CC = 3.3 V, T_A = 25°C
Typical V_OHV (Output VOH Undershoot) > 2 V at V_CC = 3.3 V, T_A = 25°C
I_off Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the V_CC Level
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model
- 1000-V Charged-Device Model

These bus transceivers are designed for 1.65-V to 3.6-V V_CC operation. The SN74LVC2G126 device is a dual line driver with 3-state output. The output is disabled when the output-enable input is low.

filter

Andere Nicht invertierende Puffer & Treiber suchen

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Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen		Datum
*	Datenblatt	SN74LVC2G126 Dual Bus Buffer Gate With 3-State Outputs datasheet (Rev. N)	PDF \| HTML		21.09.2020

Design und Entwicklung

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