SN74HC165

AKTIV

Schieberegister, 8 Bit, Parallellast

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Datenblatt

document-pdfAcrobat SNx4HC165 8-Bit Parallel-Load Shift Registers datasheet (Rev. H) (Englisch) PDF | HTML

SN74HC165

AKTIV

Jetzt bestellen

Produktdetails

Configuration

Parallel-in, Serial-out

Bits (#)

8

Technology family

HC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

24

IOL (max) (mA)

5.2

IOH (max) (mA)

-5.2

Supply current (max) (µA)

80

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

Configuration

Parallel-in, Serial-out

Bits (#)

8

Technology family

HC

Input type

Standard CMOS

Output type

Push-Pull

Clock frequency (MHz)

24

IOL (max) (mA)

5.2

IOH (max) (mA)

-5.2

Supply current (max) (µA)

80

Features

Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode

Operating temperature range (°C)

-40 to 125

Rating

Catalog

SOIC (D)

16

59.4 mm² (9.9 mm × 6 mm)

PDIP (N)

16

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

16

79.56 mm² (10.2 mm × 7.8 mm)

TSSOP (PW)

16

32 mm² (5 mm × 6.4 mm)

SSOP (DB)

16

48.36 mm² (6.2 mm × 7.8 mm)

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum I_CC
Typical t_pd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.

Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-µA Maximum I_CC
Typical t_pd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs
Parallel-to-Serial Data Conversion
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q_H) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (Q_H) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (Q_H) output. Parallel-in access to each stage is provided by eight individual direct data (A–H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (Q_H) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

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Top-Dokumentation	Typ	Titel	Format-Optionen		Datum
*	Datenblatt	SNx4HC165 8-Bit Parallel-Load Shift Registers datasheet (Rev. H)	PDF \| HTML	30.12.2015
	Application brief	Using Linear Interpolation to Estimate Specification Values	PDF \| HTML	13.04.2026
	Anwendungshinweis	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15.12.2022
	Anwendungshinweis	Increase the Number of Inputs on a Microcontroller	PDF \| HTML	27.10.2020
	Application brief	Converting SPI to GPIO Through Digital Isolators	PDF \| HTML	16.10.2020
	Anwendungshinweis	HCMOS Design Considerations (Rev. A)		09.09.2002

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SOIC (D)	16	Ultra Librarian
PDIP (N)	16	Ultra Librarian
SOP (NS)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian
SSOP (DB)	16	Ultra Librarian

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SN74HC165

Schieberegister, 8 Bit, Parallellast

SN74HC165

Produktdetails

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