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SN74CBT3125

NICHT FÜR NEUE DESIGNS EMPFOHLEN

4-Kanal-Universal-FET-Busschalter, 5 V, 1:1 (SPST) mit standardmäßiger Pinbelegung Typ 125

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Datenblatt

SN74CBT3125

NICHT FÜR NEUE DESIGNS EMPFOHLEN
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Produktdetails

Protocols Analog Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 4 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 22000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 4 Bandwidth (MHz) 200 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Operating temperature range (°C) -40 to 85 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 4 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 22000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Catalog
SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) SSOP (DBQ) 16 29.4 mm² (4.9 mm × 6 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) VQFN (RGY) 14 12.25 mm² (3.5 mm × 3.5 mm) SSOP (DB) 14 48.36 mm² (6.2 mm × 7.8 mm)
  • Standard ’125-Type Pinout (D, DB, DGV, and PW Packages)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels
  • Standard ’125-Type Pinout (D, DB, DGV, and PW Packages)
  • 5- Switch Connection Between Two Ports
  • TTL-Compatible Input Levels

The SN74CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE)\ input is high.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBT3125 quadruple FET bus switch features independent line switches. Each switch is disabled when the associated output-enable (OE)\ input is high.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt SN74CBT3125 datasheet (Rev. I) 19.09.2002

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