Produktdetails

Protocols Analog, I2C, UART Configuration 1:1 SPST Number of channels 2 Bandwidth (MHz) 500 Ron (typ) (mΩ) 4000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (µA) 700 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 8 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 9000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog, I2C, UART Configuration 1:1 SPST Number of channels 2 Bandwidth (MHz) 500 Ron (typ) (mΩ) 4000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (µA) 700 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 3.5 CON (typ) (pF) 8 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 9000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
TSSOP (PW) 8 19.2 mm² (3 mm × 6.4 mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm)
  • High-Bandwidth Data Path (up to 500MHz)
  • 5V Tolerant I/Os With Device Powered Up or Powered Down
  • Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4Ω Typ)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0 to 5V Switching With 3.3V VCC
    • 0 to 3.3V Switching With 2.5V VCC
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low Input and Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5pF Typ)
  • Fast Switching Frequency (fOE = 20MHz Max)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 0.25mA Typ)
  • VCC Operating Range From 2.3V to 3.6V
  • Data I/Os Support 0 to 5V Signaling Levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
  • Control Inputs Can Be Driven by TTL or 5V/3.3V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000V Human-Body Model (A114-B, Class II)
    • 1000V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating
  • High-Bandwidth Data Path (up to 500MHz)
  • 5V Tolerant I/Os With Device Powered Up or Powered Down
  • Low and Flat ON-State Resistance (ron) Characteristics Over Operating Range (ron = 4Ω Typ)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0 to 5V Switching With 3.3V VCC
    • 0 to 3.3V Switching With 2.5V VCC
  • Bidirectional Data Flow With Near-Zero Propagation Delay
  • Low Input and Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 3.5pF Typ)
  • Fast Switching Frequency (fOE = 20MHz Max)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 0.25mA Typ)
  • VCC Operating Range From 2.3V to 3.6V
  • Data I/Os Support 0 to 5V Signaling Levels (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 5V)
  • Control Inputs Can Be Driven by TTL or 5V/3.3V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000V Human-Body Model (A114-B, Class II)
    • 1000V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-Distortion Signal Gating

The SN74CB3Q3306A device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A device provides an optimized interface option appropriate for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3306A device is organized as two 1-bit switches with separate output-enable (1 OE, 2 OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

The SN74CB3Q3306A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To confirm the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3Q3306A device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3306A device provides an optimized interface option appropriate for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q3306A device is organized as two 1-bit switches with separate output-enable (1 OE, 2 OE) inputs. It can be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is low, the associated 1-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

The SN74CB3Q3306A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To confirm the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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* Datenblatt SN74CB3Q3306A Dual FET Bus Switch 2.5V/3.3V Low-Voltage High-Bandwidth Bus Switch datasheet (Rev. F) PDF | HTML 24.09.2026
Anwendungshinweis Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02.06.2022
Anwendungshinweis Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01.12.2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06.01.2021

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