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SN74AVCH24T245

AKTIV

Bus-Transceiver, 24 Bit, Doppelversorgung, konfigurierbare Spannungsumsetzung und Tri-State-Ausgänge

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Datenblatt

SN74AVCH24T245

AKTIV
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Produktdetails

Bits (#) 24 Data rate (max) (Mbps) 380 Topology Push-Pull Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO, JTAG, SPI, UART Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 5 Technology family AVC Supply current (max) (mA) 0.075 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 24 Data rate (max) (Mbps) 380 Topology Push-Pull Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO, JTAG, SPI, UART Features Bus-hold, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 5 Technology family AVC Supply current (max) (mA) 0.075 Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (NMU) 83 45 mm² (10 mm × 4.5 mm)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.2-V to 3.6-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6-V Tolerant
  • Bus Hold on Data Inputs, Eliminating the Need for External Pullups/Pulldowns
  • Max Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, All Outputs Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over Full 1.2-V to 3.6-V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6-V Tolerant
  • Bus Hold on Data Inputs, Eliminating the Need for External Pullups/Pulldowns
  • Max Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This 24-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH24T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH24T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCH24T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 5DIR, 6DIR, 1 OE, 2 OE, 3 OE, 4 OE, 5 OE, and 6 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This 24-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH24T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH24T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses are effectively isolated.

The SN74AVCH24T245 is designed so that the control pins (1DIR, 2DIR, 3DIR, 4DIR, 5DIR, 6DIR, 1 OE, 2 OE, 3 OE, 4 OE, 5 OE, and 6 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCCA through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt 24-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation And 3-State Outputs datasheet (Rev. C) PDF | HTML 20.08.2020
Anwendungshinweis Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02.10.2024
Anwendungshinweis Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12.07.2024
Anwendungshinweis Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03.07.2024
Auswahlhilfe Voltage Translation Buying Guide (Rev. A) 15.04.2021

Design und Entwicklung

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SN74AVCH24T245 IBIS Model (Rev. A)

SCEM465A.ZIP (70 KB) - IBIS-Modell
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