SN74ALVCH374

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Achtfaches Flipflop (Typ D), positive Flankensteuerung, mit Tri-State-Ausgängen

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Datenblatt

document-pdfAcrobat SN74ALVCH374 datasheet (Rev. G) (Englisch)

SN74ALVCH374

AKTIV

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Produktdetails

Number of channels

8

Technology family

ALVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Number of channels

8

Technology family

ALVC

Input type

Standard CMOS

Output type

3-State

Clock frequency (max) (MHz)

150

IOL (max) (mA)

24

IOH (max) (mA)

-24

Supply current (max) (µA)

10

Features

Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Operating temperature range (°C)

-40 to 85

Rating

Catalog

TVSOP (DGV)

20

32 mm² (5 mm × 6.4 mm)

TSSOP (PW)

20

41.6 mm² (6.5 mm × 6.4 mm)

SOIC (DW)

20

131.84 mm² (12.8 mm × 10.3 mm)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Operates From 1.65 V to 3.6 V
Max t_pd of 3.6 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V_CC operation.

The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to V_CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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Andere D-Typ-Flipflops suchen

Herunterladen Video mit Transkript ansehen Video

Top-Dokumentation	Typ	Titel	Format-Optionen		Datum
*	Datenblatt	SN74ALVCH374 datasheet (Rev. G)		03.09.2004
	Anwendungshinweis	Power-Up Behavior of Clocked Devices (Rev. B)	PDF \| HTML	15.12.2022
	Anwendungshinweis	An Overview of Bus-Hold Circuit and the Applications (Rev. B)		17.09.2018

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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