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DRV8329

AKTIV

Dreiphasiger intelligenter Gate-Treiber (60 V) mit drei Strom-Shunt-Verstärkern

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Datenblatt

DRV8329

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Rating Catalog Architecture Gate driver Control interface 3xPWM, 6xPWM Vs (min) (V) 4.5 Vs ABS (max) (V) 65 Features 1x low side current sense, Bootstrap Architecture for Gate Driver, HW based configuration, Supports 100% PWM Duty Cycle with Trickle Charge pump Operating temperature range (°C) -40 to 125
Rating Catalog Architecture Gate driver Control interface 3xPWM, 6xPWM Vs (min) (V) 4.5 Vs ABS (max) (V) 65 Features 1x low side current sense, Bootstrap Architecture for Gate Driver, HW based configuration, Supports 100% PWM Duty Cycle with Trickle Charge pump Operating temperature range (°C) -40 to 125
WQFN (REE) 36 20 mm² (4 mm × 5 mm)
  • 65-V Three Phase Half-Bridge Gate Driver
    • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
    • 4.5 to 60-V Operating Voltage Range
    • Supports 100% PWM Duty Cycle with Trickle Charge pump
  • Bootstrap based Gate Driver Architecture
    • 1000-mA Maximum Peak Source Current
    • 2000-mA Maximum Peak Sink Current
  • Integrated Current Sense Amplifier with low input offset (optimized for 1 shunt)
    • Adjustable Gain (5, 10, 20, 40 V/V)
  • Hardware interface provides simple configuration
  • Ultra-low power sleep mode <1 uA at 25 ̊C
  • 4-ns (typ) propagation delay matching between phases
  • Independent driver shutdown path (DRVOFF)
  • 65-V tolerant wake pin (nSLEEP)
  • Supports negative transients upto -10V on SHx
  • 6x and 3x PWM Modes
  • Supports 3.3-V, and 5-V Logic Inputs
  • Accurate LDO (AVDD), 3.3 V ±3%, 80 mA
  • Compact QFN Packages and Footprints
  • Adjustable VDS overcurrent threshold through VDSLVL pin
  • Adjustable deadtime through DT pin
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
    • PVDD Undervoltage Lockout (PVDDUV)
    • GVDD Undervoltage (GVDDUV)
    • Bootstrap Undervoltage (BST_UV)
    • Overcurrent Protection (VDS_OCP, SEN_OCP)
    • Thermal Shutdown (OTSD)
    • Fault Condition Indicator (nFAULT)
  • 65-V Three Phase Half-Bridge Gate Driver
    • Drives 3 High-Side and 3 Low-Side N-Channel MOSFETs (NMOS)
    • 4.5 to 60-V Operating Voltage Range
    • Supports 100% PWM Duty Cycle with Trickle Charge pump
  • Bootstrap based Gate Driver Architecture
    • 1000-mA Maximum Peak Source Current
    • 2000-mA Maximum Peak Sink Current
  • Integrated Current Sense Amplifier with low input offset (optimized for 1 shunt)
    • Adjustable Gain (5, 10, 20, 40 V/V)
  • Hardware interface provides simple configuration
  • Ultra-low power sleep mode <1 uA at 25 ̊C
  • 4-ns (typ) propagation delay matching between phases
  • Independent driver shutdown path (DRVOFF)
  • 65-V tolerant wake pin (nSLEEP)
  • Supports negative transients upto -10V on SHx
  • 6x and 3x PWM Modes
  • Supports 3.3-V, and 5-V Logic Inputs
  • Accurate LDO (AVDD), 3.3 V ±3%, 80 mA
  • Compact QFN Packages and Footprints
  • Adjustable VDS overcurrent threshold through VDSLVL pin
  • Adjustable deadtime through DT pin
  • Efficient System Design With Power Blocks
  • Integrated Protection Features
    • PVDD Undervoltage Lockout (PVDDUV)
    • GVDD Undervoltage (GVDDUV)
    • Bootstrap Undervoltage (BST_UV)
    • Overcurrent Protection (VDS_OCP, SEN_OCP)
    • Thermal Shutdown (OTSD)
    • Fault Condition Indicator (nFAULT)

The DRV8329 family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The device generates the correct gate drive voltages using an internal charge pump and enhances the high-side MOSFETs using a bootstrap circuit. A trickle charge pump is included to support 100% duty cycle. The Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A sink. The DRV8329 can operate from a single power supply and supports a wide input supply range of 4.5 to 60 V.

The 6x and 3x PWM modes allow for simple interfacing to controller circuits. The device has integrated accurate 3.3-V LDO that can be used to power external controller and can be used as reference for CSA. The configuration settings for the device are configurable through hardware (H/W) pins.

The DRV8329 devices integrate low-side current sense amplifier that allow current sensing for sum of current from all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, GVDD fault, MOSFET overcurrent, MOSFET short circuit, and overtemperature. Fault conditions are indicated on nFAULT pin.

The DRV8329 family of devices is an integrated gate driver for three-phase applications. The devices provide three half-bridge gate drivers, each capable of driving high-side and low-side N-channel power MOSFETs. The device generates the correct gate drive voltages using an internal charge pump and enhances the high-side MOSFETs using a bootstrap circuit. A trickle charge pump is included to support 100% duty cycle. The Gate Drive architecture supports peak gate drive currents up to 1-A source and 2-A sink. The DRV8329 can operate from a single power supply and supports a wide input supply range of 4.5 to 60 V.

The 6x and 3x PWM modes allow for simple interfacing to controller circuits. The device has integrated accurate 3.3-V LDO that can be used to power external controller and can be used as reference for CSA. The configuration settings for the device are configurable through hardware (H/W) pins.

The DRV8329 devices integrate low-side current sense amplifier that allow current sensing for sum of current from all three phases of the drive stage.

A low-power sleep mode is provided to achieve low quiescent current by shutting down most of the internal circuitry. Internal protection functions are provided for undervoltage lockout, GVDD fault, MOSFET overcurrent, MOSFET short circuit, and overtemperature. Fault conditions are indicated on nFAULT pin.
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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DRV8329 4.5 to 60 V Three-phase BLDC Gate Driver datasheet (Rev. B) PDF | HTML 16.12.2024
Technischer Artikel Selecting the right level of integration to meet motor design requirements PDF | HTML 04.01.2024
Anwendungshinweis Power Delivery in Cordless Power Tools Using DRV8329 PDF | HTML 15.09.2022
Zertifikat DRV8329AEVM EU RoHS Declaration of Conformity (DoC) 22.03.2022

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