CD74HC4046A

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Highspeed-CMOS-Logik-Phasenregelschleife mit VCO

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Datenblatt

document-pdfAcrobat CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A datasheet (Rev. J) (Englisch)

CD74HC4046A

AKTIV

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Produktdetails

Technology family

HC

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

HC

Bits (#)

1

Rating

Catalog

Operating temperature range (°C)

-55 to 125

PDIP (N)

16

181.42 mm² (19.3 mm × 9.4 mm)

TSSOP (PW)

16

32 mm² (5 mm × 6.4 mm)

SOIC (D)

16

59.4 mm² (9.9 mm × 6 mm)

SOP (NS)

16

79.56 mm² (10.2 mm × 7.8 mm)

Operating Frequency Range
- Up to 18MHz (Typ) at V_CC = 5V
- Minimum Center Frequency of 12MHz at V_CC = 4.5V
Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
Minimal Frequency Drift
Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at VOL, VOH
Applications
- FM Modulation and Demodulation
- Frequency Synthesis and Multiplication
- Frequency Discrimination
- Tone Decoding
- Data Synchronization and Conditioning
- Voltage-to-Frequency Conversion
- Motor-Speed Control

Operating Frequency Range
- Up to 18MHz (Typ) at V_CC = 5V
- Minimum Center Frequency of 12MHz at V_CC = 4.5V
Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
VCO-Inhibit Control for ON/OFF Keying and for Low Standby Power Consumption
Minimal Frequency Drift
Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55°C to 125°C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at VOL, VOH
Applications
- FM Modulation and Demodulation
- Frequency Synthesis and Multiplication
- Frequency Discrimination
- Tone Decoding
- Data Synchronization and Conditioning
- Voltage-to-Frequency Conversion
- Motor-Speed Control

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

The ’HC4046A and ’HCT4046A are high-speed silicon-gate CMOS devices that are pin compatible with the CD4046B of the "4000B" series. They are specified in compliance with JEDEC standard number 7.

The ’HC4046A and ’HCT4046A are phase-locked-loop circuits that contain a linear voltage-controlled oscillator (VCO) and three different phase comparators (PC1, PC2 and PC3). A signal input and a comparator input are common to each comparator.

The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 4046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.

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Top-Dokumentation	Typ	Titel		Datum
*	Datenblatt	CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A datasheet (Rev. J)	21.11.2003
	Anwendungshinweis	Implementation of FSK Modulation and Demodulation using CD74HC4046A	25.11.2013
	Anwendungshinweis	Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency	31.03.2008
	Anwendungshinweis	CMOS Phase-Locked-Loop Applications (Rev. B)	19.09.2002

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
PDIP (N)	16	Ultra Librarian
TSSOP (PW)	16	Ultra Librarian
SOIC (D)	16	Ultra Librarian
SOP (NS)	16	Ultra Librarian

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CD74HC4046A

Highspeed-CMOS-Logik-Phasenregelschleife mit VCO

CD74HC4046A

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