CD4030B

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Vierfach-XOR-Gatter mit 2 Eingängen, 3 V bis 18 V

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Datenblatt

document-pdfAcrobat CD4030B TYPES datasheet (Rev. C) (Englisch)

CD4030B

AKTIV

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Produktdetails

Technology family

CD4000

Number of channels

4

Inputs per channel

2

IOL (max) (mA)

6.8

Input type

Standard CMOS

IOH (max) (mA)

-6.8

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

4

Inputs per channel

2

IOL (max) (mA)

6.8

Input type

Standard CMOS

IOH (max) (mA)

-6.8

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Catalog

Operating temperature range (°C)

-55 to 125

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

PDIP (N)

14

181.42 mm² (19.3 mm × 9.4 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

Medium-speed operation—t_PHL, t_PLH = 65 ns (typ.) at V_DD = 10 V, C_L = 50 pF
100% tested for quiescent current at 20 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range) =
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Even and odd-parity generators and checkers
- Logical comparators
- Adders/subtractors
- General logic functions

Data sheet acquired from Harris Semiconductor

Medium-speed operation—t_PHL, t_PLH = 65 ns (typ.) at V_DD = 10 V, C_L = 50 pF
100% tested for quiescent current at 20 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range) =
     1 V at V_DD = 5 V
     2 V at V_DD = 10 V
  2.5 V at V_DD = 15 V
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Even and odd-parity generators and checkers
- Logical comparators
- Adders/subtractors
- General logic functions

Data sheet acquired from Harris Semiconductor

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function.

The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function.

The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Andere XOR-Gatter (Exklusives OR) suchen

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Neueste englische Version herunterladen		Datum
*	Datenblatt	CD4030B TYPES datasheet (Rev. C)			21.08.2003

Design und Entwicklung

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Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

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