The AFE7906 is a high
performance, wide bandwidth multi-channel receiver, integrating six RF Sampling
ADCs. With operation up to 12GHz, this device enables direct RF sampling in the L,
S, C and X-band frequency ranges without the need for additional frequency
conversions stages. This improvement in density and flexibility enables
high-channel-count, multi-mission systems.
Each receiver chain includes a 25dB range DSA
(Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter).
Four receiver channels have an analog peak power detector and various digital power
detectors to assist an external or internal autonomous automatic gain controller,
and RF overload detectors for device reliability protection. Flexible decimation
options provide optimization of data bandwidth up to 1200MHz for four RX or
600MHz.
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a
3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak
power detector and various digital power detectors to assist an external or internal
autonomous automatic gain controller, and RF overload detectors for device
reliability protection. Flexible decimation options provide optimization of data
bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths
(1200MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF
input timing relative to the device clock.
The AFE7906 is a high
performance, wide bandwidth multi-channel receiver, integrating six RF Sampling
ADCs. With operation up to 12GHz, this device enables direct RF sampling in the L,
S, C and X-band frequency ranges without the need for additional frequency
conversions stages. This improvement in density and flexibility enables
high-channel-count, multi-mission systems.
Each receiver chain includes a 25dB range DSA
(Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter).
Four receiver channels have an analog peak power detector and various digital power
detectors to assist an external or internal autonomous automatic gain controller,
and RF overload detectors for device reliability protection. Flexible decimation
options provide optimization of data bandwidth up to 1200MHz for four RX or
600MHz.
The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.
Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a
3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak
power detector and various digital power detectors to assist an external or internal
autonomous automatic gain controller, and RF overload detectors for device
reliability protection. Flexible decimation options provide optimization of data
bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths
(1200MHz BW each).
The device contains a SYSREF timing detector to allow optimization of the SYSREF
input timing relative to the device clock.