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Highspeed-ADCs (≥ 10 MSPS)

ADC12DJ3200QML-SP

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ADC strahlungshärtegesichert (RHA), QMLV, 300 krad, 12 Bit, 3,2 GSPS zweifach oder 6,4 GSPS einzeln

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ADC12DJ3200QML-SP

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Produktdetails

Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
Sample rate (max) (Msps) 3200, 6400 Resolution (Bits) 12 Number of input channels 1, 2 Interface type JESD204B Analog input BW (MHz) 7300 Features Ultra High Speed Rating Space Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 3000 Architecture Folding Interpolating SNR (dB) 57.2 ENOB (Bits) 8.9 SFDR (dB) 76 Operating temperature range (°C) -55 to 125 Input buffer Yes Radiation, TID (typ) (krad) 300 Radiation, SEL (MeV·cm2/mg) 120
CCGA-FC (NWE) 196 225 mm² 15 x 15
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W
  • ADC core:
    • 12-Bit resolution
    • Up to 6.4GSPS in single-channel mode
    • Up to 3.2GSPS in dual-channel mode
  • Noise floor (no signal, VFS = 1VPP-DIFF):
    • Dual-channel mode: –149.5dBFS/Hz
    • Single-channel mode: –152.4dBFS/Hz
  • Peak noise power ratio (NPR): 45.4dB
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 7GHz
    • Usable input frequency range: >10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs step size
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204B subclass-1 compliant interface:
    • Maximum lane rate: 12.8Gbps
    • Up to 16 lanes allows reduced lane rate
  • Digital down-converters in dual-channel mode:
    • Real output: DDC bypass or 2x decimation
    • Complex output: 4x, 8x, or 16x decimation
  • Radiation performance:
    • Total Ionizing Dose (TID): 300krad (Si)
    • Single Event Latchup (SEL): 120MeV-cm2/mg
    • Single Event Upset (SEU) immune registers
  • Power consumption: 3W

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).

The ADC12DJ3200QML-SP device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from dc to above 10GHz. In dual-channel mode, the ADC12DJ3200QML-SP can sample up to 3200MSPS. In single-channel mode, the device can sample up to 6400MSPS. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3dB) of 7GHz, with usable frequencies exceeding the –3dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC12DJ3200QML-SP uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multidevice synchronization. The serial output lanes support up to 12.8Gbps, and can be configured to trade off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for synthetic aperture radar (SAR) and phased-array MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Datum
* Data sheet ADC12DJ3200QML-SP 6.4GSPS, Single-Channel or 3.2GSPS, Dual-Channel, 12-Bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. C) PDF | HTML 21 Mär 2025
* SMD ADC12DJ3200QML-SP SMD ADC12DJ3200QML-SP SMD 5962-18209 04 Aug 2020
* Radiation & reliability report ADC12DJ3200QML-SP - Single-Event Effects (SEE) Radiation Test Report 03 Aug 2020
* Radiation & reliability report Analysis of Low Dose Rate Effects on Parasitic Bipolar Structures in CMOS Proces 04 Mai 2012
Selection guide TI Space Products (Rev. L) 27 Mär 2026
Application brief DLA Approved Optimizations for QML Products (Rev. C) PDF | HTML 17 Jun 2025
Application note Heavy Ion Orbital Environment Single-Event Effects Estimations (Rev. B) PDF | HTML 10 Jun 2025
More literature TI Engineering Evaluation Units vs. MIL-PRF-38535 QML Class V Processing (Rev. B) 20 Feb 2025
Application note Single-Event Effects Confidence Interval Calculations (Rev. A) PDF | HTML 19 Okt 2022
Technical article How SHP in plastic packaging addresses 3 key space application design challenges PDF | HTML 17 Okt 2022

Design und Entwicklung

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Evaluierungsplatine

ADC12DJ3200EVMCVAL — ADC12DJ3200QML-SP-Evaluierungsmodul

Das ADC12DJ3200 Evaluierungsmodul (EVM) wurde entwickelt, um die ADC12DJ3200QML-SP hochgeschwindigkeits Analog-Digital-Wandler (ADCs) zu bewerten. Das Evaluierungsmodul ist mit dem ADC12DJ3200QML-SP bestückt, einem hochbelastbaren 12-Bit, Dual-Channel 4 GSPS oder Single-Channel 8 GSPS ADC mit (...)
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Firmware

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model

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Simulationsmodell

ADC12DJ3200QML-SP S-Parameter Model

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Montagezeichnung

ADC12DJ3200QML-EVM Assembly Package

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ADC12DJ3200EVMCVAL Design Files

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