ADC08DJ5200RF

AKTIV

Produktdetails

Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 8100 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 3700 Architecture Folding Interpolating SNR (dB) 48.8 ENOB (Bits) 7.8 SFDR (dB) 65 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 5200, 10400 Resolution (Bits) 8 Number of input channels 1, 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 8100 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.825 Power consumption (typ) (mW) 3700 Architecture Folding Interpolating SNR (dB) 48.8 ENOB (Bits) 7.8 SFDR (dB) 65 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² (10 mm × 10 mm)
  • ADC core:
    • 8-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –143.4dBFS/Hz
      • Single-channel mode: –146.2dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz, TYP): 7.8 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8.1GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.8W
  • Power supplies: 1.1V, 1.9V
  • ADC core:
    • 8-bit resolution
    • Up to 10.4GSPS in single-channel mode
    • Up to 5.2GSPS in dual-channel mode
  • Performance specifications:
    • Noise floor (–20dBFS, VFS = 1 VPP-DIFF):
      • Dual-channel mode: –143.4dBFS/Hz
      • Single-channel mode: –146.2dBFS/Hz
    • ENOB (dual channel, FIN = 2.4GHz, TYP): 7.8 Bits
  • Buffered analog inputs with VCMI of 0V:
    • Analog input bandwidth (–3dB): 8.1GHz
    • Usable input frequency range: > 10GHz
    • Full-scale input voltage (VFS, default): 0.8VPP
  • Noiseless aperture delay (tAD) adjustment:
    • Precise sampling control: 19fs Step
    • Simplifies synchronization and interleaving
    • Temperature and voltage invariant delays
  • Easy-to-use synchronization features:
    • Automatic SYSREF timing calibration
    • Timestamp for sample marking
  • JESD204C serial data interface:
    • Maximum lane rate: 17.16Gbps
    • Support for 64b/66b and 8b/10b encoding
    • 8b/10b modes are JESD204B compatible
  • Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
  • Programmable FIR filter for equalization
  • Power consumption: 3.8W
  • Power supplies: 1.1V, 1.9V

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.

The ADC08DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that directly samples input frequencies from DC to above 10GHz. The ADC08DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

The ADC08DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. A programmable FIR filter allows on-chip equalization.

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* Datenblatt ADC08DJ5200RF 10.4GSPS Single-Channel or 5.2GSPS Dual-Channel, 8-bit, RF-Sampling Analog-to-Digital Converter (ADC) datasheet (Rev. B) PDF | HTML 08.04.2025
Anwendungshinweis Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends PDF | HTML 28.03.2025
Anwendungshinweis Evaluating High-Speed, RF ADC Converter Front-end Architectures PDF | HTML 26.03.2025

Design und Entwicklung

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Evaluierungsplatine

ADC08DJ5200RFEVM — ADC08DJ5200RF – Evaluierungsmodul für 8-Bit-ADC mit HF-Abtastung und zwei 5,2-GSPS oder einem 10,4-G

Das ADC08DJ5200RF-Evaluierungsmodul (EVM) ist eine Plattform zur Evaluierung der Leistung des ADC08DJ5200RF. Der ADC08DJ5200RF ist ein stromsparender 8-Bit-Analog-Digital-Wandler (ADC) mit zwei Kanälen und 5,2 GSPS oder einem Kanal und 10,4 GSPS mit HF-Abtastung, einem gepufferten Analogeingang und (...)

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Die JESD204 Rapid Design IP ist dazu entwickelt worden, FPGA-Technikern einen beschleunigten Weg zu einem funktionierenden JESD204-System zu ermöglichen. Diese IP ist derart ausgelegt worden, dass nachgelagerte digitale Verarbeitung und sonstige Anwendungslogik von den meisten leistungs- und (...)

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Berechnungstool

ADC12DJ5200RF-CALC — Vollausschlag-Berechnungstool für ADC12DJ5200RF-Eingangsnetzwerk.

Calculation tool referenced in application note SLVAFZ7.
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FCCSP (AAV) 144 Ultra Librarian

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