DS92LX2121

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10MHz 至 50MHz 直流平衡 Channel Link III 双向控制串行器

产品详情

Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
Protocols Catalog Rating Catalog Operating temperature range (°C) -40 to 85
WQFN (RTA) 40 36 mm² 6 x 6
  • General
    • Up to 1050 Mbits/sec Data Throughput
    • 10 MHz to 50 MHz Input Clock Support
    • Supports 18-bit Color Depth
      (RGB666 + HS, VS, DE)
    • Embedded Clock with DC Balanced Coding to
      Support AC-Coupled Interconnects
    • Capable to Drive up to 10 Meters Shielded
      Twisted-Pair
    • Bi-Directional Control Interface Channel
      with I2C Support
    • I2C Interface for Device
      Configuration. Single-Pin ID Addressing
    • Up to 4 GPI on DES and GPO on SER
    • AT-SPEED BIST Diagnosis Feature to Validate
      Link Integrity
    • Individual Power-Down Controls for both SER
      and DES
    • User-Selectable Clock Edge for Parallel Data
      on both SER and DES
    • Integrated Termination Resistors
    • 1.8V- or 3.3V-Compatible Parallel Bus Interface
    • Single Power Supply at 1.8V
    • IEC 61000–4–2 ESD Compliant
    • Temperature Range −40°C to +85°C
  • DESERIALIZER — DS92LX2122
    • No Reference Clock Required on Deserializer
    • Programmable Receive Equalization
    • LOCK Output Reporting Pin to Ensure
    • EMI/EMC Mitigation
      • Programmable Spread Spectrum (SSCG) Outputs
      • Receiver Output Drive Strength Control (RDS)
      • Receiver Staggered Outputs
  • General
    • Up to 1050 Mbits/sec Data Throughput
    • 10 MHz to 50 MHz Input Clock Support
    • Supports 18-bit Color Depth
      (RGB666 + HS, VS, DE)
    • Embedded Clock with DC Balanced Coding to
      Support AC-Coupled Interconnects
    • Capable to Drive up to 10 Meters Shielded
      Twisted-Pair
    • Bi-Directional Control Interface Channel
      with I2C Support
    • I2C Interface for Device
      Configuration. Single-Pin ID Addressing
    • Up to 4 GPI on DES and GPO on SER
    • AT-SPEED BIST Diagnosis Feature to Validate
      Link Integrity
    • Individual Power-Down Controls for both SER
      and DES
    • User-Selectable Clock Edge for Parallel Data
      on both SER and DES
    • Integrated Termination Resistors
    • 1.8V- or 3.3V-Compatible Parallel Bus Interface
    • Single Power Supply at 1.8V
    • IEC 61000–4–2 ESD Compliant
    • Temperature Range −40°C to +85°C
  • DESERIALIZER — DS92LX2122
    • No Reference Clock Required on Deserializer
    • Programmable Receive Equalization
    • LOCK Output Reporting Pin to Ensure
    • EMI/EMC Mitigation
      • Programmable Spread Spectrum (SSCG) Outputs
      • Receiver Output Drive Strength Control (RDS)
      • Receiver Staggered Outputs

The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.

In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.

The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.

The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.

In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.

The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.

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类型 标题 下载最新的英语版本 日期
* 数据表 DS92LX2121/22 10 - 50 MHz DC-Balanced Ch Link III Bi-Directional Control SER/DES 数据表 (Rev. J) 2014年 1月 17日
应用手册 High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 2018年 11月 9日
应用手册 DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013年 4月 29日
用户指南 LX21EVK01 Channel Link III Ser/Des Evaluation Kit 2012年 2月 1日
应用手册 App Note 1909 DS15BA101 & DS15EA101 Enable Long Reach Apps for Embed Clk SERDES 2009年 3月 2日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

LX21EVK01 — LX21EVK01 评估套件

The LX21EVK01 is an evaluation kit designed to demonstrate the performance and capabilities of the DS92LX2121 and DS92LX2122 Channel Link III Serializer/Deserializer chipset.

The DS92LX2121 serializer board accepts LVCMOS input signals for the high speed forward channel and provides additional (...)

用户指南: PDF
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仿真模型

DS92LX2121 IBIS Model

SNLM109.ZIP (144 KB) - IBIS Model
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用户指南: PDF
英语版 (Rev.A): PDF
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WQFN (RTA) 40 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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