DS90UR124

正在供货

5-43MHz DC 平衡 24 位 FPD 链接 II 解串器

产品详情

Function Deserializer Color depth (bps) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication EMI reduction LVDS Diagnostics BIST Rating Catalog Operating temperature range (°C) -40 to 105
Function Deserializer Color depth (bps) 18 Input compatibility FPD-Link LVDS Output compatibility LVCMOS Features Low-EMI Point-to-Point Communication EMI reduction LVDS Diagnostics BIST Rating Catalog Operating temperature range (°C) -40 to 105
TQFP (PAG) 64 144 mm² 12 x 12
  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2
    Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports
    AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM
    ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread
    Spectrum Input; Data Randomization and
    Shuffling on Serial Link; Deserializer Provides
    Adjustable PTO (Progressive Turnon) LVCMOS
    Outputs
  • @Speed BIST (Built-In Self-Test) to Validate
    LVDS Transmission Path
  • Individual Power-Down Controls for Both
    Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin
    TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With
    DS90C241/DS90C124
  • Supports Displays With 18-Bit Color Depth
  • 5-MHz to 43-MHz Pixel Clock
  • Automotive-Grade Product AEC-Q100 Grade 2
    Qualified
  • 24:1 Interface Compression
  • Embedded Clock With DC Balancing Supports
    AC-Coupled Data Transmission
  • Capable to Drive up to 10 Meters Shielded
    Twisted-Pair Cable
  • No Reference Clock Required (Deserializer)
  • Meets ISO 10605 ESD – Greater than 8 kV HBM
    ESD Structure
  • Hot Plug Support
  • EMI Reduction – Serializer Accepts Spread
    Spectrum Input; Data Randomization and
    Shuffling on Serial Link; Deserializer Provides
    Adjustable PTO (Progressive Turnon) LVCMOS
    Outputs
  • @Speed BIST (Built-In Self-Test) to Validate
    LVDS Transmission Path
  • Individual Power-Down Controls for Both
    Transmitter and Receiver
  • Power Supply Range 3.3 V ±10%
  • 48-Pin TQFP Package for Transmitter and 64-Pin
    TQFP Package for Receiver
  • Temperature Range: –40°C to 105°C
  • Backward-Compatible Mode With
    DS90C241/DS90C124

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is ideally suited for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.

In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.

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DS90UR124-Q1 正在供货 5MHz 至 43MHz 直流平衡 24 位 FPD-Link II 解串器 - 汽车级 Automotive grade version

技术文档

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类型 标题 下载最新的英语版本 日期
* 数据表 DS90URxxx-Q1 5-MHz to 43-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset 数据表 (Rev. O) PDF | HTML 2015年 4月 29日
应用手册 DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013年 4月 29日
应用手册 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) 2013年 4月 29日
应用手册 AN-1807 FPD-Link II Display SerDes Overview (Rev. B) 2013年 4月 26日
应用手册 AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B) 2013年 4月 26日
应用手册 Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) 2013年 4月 26日
用户指南 High Efficiency Portable Media Player (PMP) Dock Station User Guide 2012年 1月 27日
用户指南 DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide 2012年 1月 26日
用户指南 FPD to SERDES (UR) Translator Chip DS99R421 Evaluation Kit User's Guide 2012年 1月 26日
应用手册 Application Note 1807 FPD-Link II Display SerDes Overview (cn) 2009年 11月 4日
应用手册 App Note 1909 DS15BA101 & DS15EA101 Enable Long Reach Apps for Embed Clk SERDES 2009年 3月 2日
应用手册 LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (cn) 最新英语版本 (Rev.A) 2008年 9月 4日
应用手册 App Note 1826 Extending Reach of a FPD-Link II Intrfce w/Cable Drvrs & Equalzr 最新英语版本 (Rev.A) 2008年 3月 24日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

SERDESUR-43USB — 用于 DS90UR241 DS90UR124 串行器和解串器芯片组的评估板

The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.

The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. (...)

用户指南: PDF
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用户指南: PDF
英语版 (Rev.A): PDF
封装 引脚 下载
TQFP (PAG) 64 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

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