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CDCUA877

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适用于 DDR2 SDRAM 应用的 1.8V/1.9V 锁相环路时钟驱动器

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CDCUA877

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Function Memory interface Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 410 Number of outputs 10 Output supply voltage (V) 1.8 Core supply voltage (V) 1.8 Output skew (ps) 30 Features DDR2 PLL Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS
Function Memory interface Additive RMS jitter (typ) (fs) 40 Output frequency (max) (MHz) 410 Number of outputs 10 Output supply voltage (V) 1.8 Core supply voltage (V) 1.8 Output skew (ps) 30 Features DDR2 PLL Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVCMOS Input type LVCMOS
NFBGA (NMK) 52 31.5 mm² 7 x 4.5
  • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 125 MHz to 410 MHz
  • Application Frequency: 160 MHz to 410 MHz
  • Low Current Consumption: <200 mA Typ
  • Low Jitter (Cycle-Cycle): ±40 ps
  • Low Output Skew: 35 ps
  • Stabilization Time <6 µs
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • 52-Ball µBGA (MicroStar Junior™ BGA, 0,65-mm pitch)
  • External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clockst
  • Meets or Exceeds CUA877/CAU878 Specification PLL Standard for PC2-3200/4300/5300/6400o
  • Fail-Safe Inputs

MicroStar Junior is a trademark of Texas Instruments.
  • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications
  • Spread Spectrum Clock Compatible
  • Operating Frequency: 125 MHz to 410 MHz
  • Application Frequency: 160 MHz to 410 MHz
  • Low Current Consumption: <200 mA Typ
  • Low Jitter (Cycle-Cycle): ±40 ps
  • Low Output Skew: 35 ps
  • Stabilization Time <6 µs
  • Distributes One Differential Clock Input to Ten Differential Outputs
  • 52-Ball µBGA (MicroStar Junior™ BGA, 0,65-mm pitch)
  • External Feedback Pins (FBIN, FBIN) are Used to Synchronize the Outputs to the Input Clockst
  • Meets or Exceeds CUA877/CAU878 Specification PLL Standard for PC2-3200/4300/5300/6400o
  • Fail-Safe Inputs

MicroStar Junior is a trademark of Texas Instruments.

The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.

The CDCUA877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C).

The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.

The CDCUA877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C).
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类型 标题 下载最新的英语版本 日期
* 数据表 1.8-V Phase Lock Loop Clock Driver 数据表 (Rev. A) 2007年 6月 18日
* 用户指南 CTS MicroStar BGA Discontinued and Redesigned 2022年 5月 8日
应用手册 DDR2 Memory Interface Clocks and Registers - Overview 2009年 3月 25日
应用手册 Application Examples for CDCUx877x PLL family 2008年 5月 7日

设计和开发

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仿真模型

CDCUA877 IBIS Model

SCAC085.ZIP (13 KB) - IBIS Model
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包含信息：
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  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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