产品详情

Number of channels 8 Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 8 Technology family AC Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 20 167.464 mm² 24.2 x 6.92
  • Buffered inputs
  • Typical pro-agation delay:
    4.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST* ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

*FAST is a Registered Trademark of Fairchild Semicondutor Corp.

  • Buffered inputs
  • Typical pro-agation delay:
    4.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST* ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

*FAST is a Registered Trademark of Fairchild Semicondutor Corp.

The RCA-CD54/74AC373 and CD54/74AC533 and the CD54/74ACT373 and CD54/74ACT533 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\) is HIGH. When the Latch Enable (LE\) goes LOW, the data is latched. The Output Enable (OE\) controls the 3-sate outputs. When the Output Enable (OE\) is HIGH, the outputs are in the high-impedance state. The latch operation is independent of the state of the Output Enable.

The CD74AC/ACT373 and CD74AC/ACT533 are supplied in 20-lead dual-in-line plastic package (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commerical (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT373 and CD54AC/ACT533, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

The RCA-CD54/74AC373 and CD54/74AC533 and the CD54/74ACT373 and CD54/74ACT533 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\) is HIGH. When the Latch Enable (LE\) goes LOW, the data is latched. The Output Enable (OE\) controls the 3-sate outputs. When the Output Enable (OE\) is HIGH, the outputs are in the high-impedance state. The latch operation is independent of the state of the Output Enable.

The CD74AC/ACT373 and CD74AC/ACT533 are supplied in 20-lead dual-in-line plastic package (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Commerical (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT373 and CD54AC/ACT533, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

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类型 标题 下载最新的英语版本 日期
* 数据表 Octal Transparent Latch, 3-State 数据表 1998年 12月 3日
应用手册 Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
选择指南 Logic Guide (Rev. AB) 2017年 6月 12日
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
选择指南 逻辑器件指南 2014 (Rev. AA) 最新英语版本 (Rev.AB) 2014年 11月 17日
更多文献资料 HiRel Unitrode Power Management Brochure 2009年 7月 7日
用户指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
应用手册 Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
应用手册 使用逻辑器件进行设计 (Rev. C) 1997年 6月 1日
应用手册 Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
应用手册 Live Insertion 1996年 10月 1日
应用手册 Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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