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模数转换器 (ADC)
高速 ADC (≥10MSPS)

ADC08D1500

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8 位、双路 1.5GSPS 或单路 3.0GSPS 模数转换器 (ADC)

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ADC08D1500

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产品详情

Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 8 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 47 ENOB (bit) 7.4 SFDR (dB) 56 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 1500, 3000 Resolution (Bits) 8 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 1700 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.87 Power consumption (typ) (mW) 1800 Architecture Folding Interpolating SNR (dB) 47 ENOB (bit) 7.4 SFDR (dB) 56 Operating temperature range (°C) -40 to 85 Input buffer No
HLQFP (NNB) 128 484 mm² 22 x 22
  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Ensured No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 1.5 GSPS (min)
  • Error Rate 10-18 (typ)
  • ENOB @ 748 MHz Input 7.25 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating 1.8 W (typ)
    • Power Down Mode 3.5 mW (typ)

All trademarks are the property of their respective owners.

  • Internal Sample-and-Hold
  • Single +1.9V ±0.1V Operation
  • Choice of SDR or DDR Output Clocking
  • Interleave Mode for 2x Sample Rate
  • Multiple ADC Synchronization Capability
  • Ensured No Missing Codes
  • Serial Interface for Extended Control
  • Fine Adjustment of Input Full-Scale Range and Offset
  • Duty Cycle Corrected Sample Clock

Key Specifications

  • Resolution 8 Bits
  • Max Conversion Rate 1.5 GSPS (min)
  • Error Rate 10-18 (typ)
  • ENOB @ 748 MHz Input 7.25 Bits (typ)
  • DNL ±0.15 LSB (typ)
  • Power Consumption
    • Operating 1.8 W (typ)
    • Power Down Mode 3.5 mW (typ)

All trademarks are the property of their respective owners.

The ADC08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 C.E.R. Output formatting is binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.

The ADC08D1500 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.8 Watts at 1.5 GSPS from a single 1.9 Volt supply, this device is ensured to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.25 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 C.E.R. Output formatting is binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sample rate. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA ≤ +85°C) temperature range.
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类型 标题 下载最新的英语版本 日期
* 数据表 ADC08D1500 High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Converter 数据表 (Rev. G) 2013年 4月 18日
应用手册 AN-1558 Clocking High-Speed A/D Converters (Rev. B) 2013年 5月 1日
应用手册 Generating Precision Clocks for Time- Interleaved ADCs 2007年 8月 2日
应用手册 Application Note 1558 Clocking High-Speed A/D Converters (cn) 2007年 3月 17日
白皮书 High-Performance Analog Front Ends 2006年 1月 1日
应用手册 Understanding High-Speed Signals, Clocks, and Data Capture 2005年 10月 18日
应用手册 Send High-Speed ADC Data Remotely And Quietly Using LVDS 2003年 3月 27日

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仿真模型

ADC08D1500 IBIS Model

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  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
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  • 封装厂地点

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