TPS51100

正在供货

3A 拉电流/灌电流 DDR 终端器稳压器

产品详情

Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 0.75 Vout (max) (V) 1.25 Features S3/S5 Support Iq (typ) (mA) 0.5 Rating Catalog Operating temperature range (°C) -40 to 85 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, LPDDR3
HVSSOP (DGQ) 10 14.7 mm² 3 x 4.9
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications
  • Input Voltage Range: 4.75 V to 5.25 V
  • VLDOIN Voltage Range: 1.2 V to 3.6 V
  • 3-A Sink/Source Termination Regulator
    Includes Droop Compensation
  • Requires Only 20-μF Ceramic Output
    Capacitance
  • Supports Hi-Z in S3 and Soft-Off in S5
  • 1.2-V Input (VLDOIN) Helps Reduce Total
    Power Dissipation
  • Integrated Divider Tracks 0.5 VDDQSNS for
    VTT and VTTREF
  • Remote Sensing (VTTSNS)
  • ±20-mV Accuracy for VTT and VTTREF
  • 10-mA Buffered Reference (VTTREF)
  • Built-In Soft-Start, UVLO, and OCL
  • Thermal Shutdown
  • Supports JEDEC Specifications

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

The TPS51100 is a 3-A, sink/source tracking termination regulator. The device is specifically designed for low-cost and low-external component count systems where space is a premium.

The TPS51100 maintains fast transient response, only requiring 20 µF (2 × 10 µF) of ceramic output capacitance. The TPS51100 supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. The part also supports DDR3 VTT termination with VDDQ at 1.5 V (typical). In addition, the TPS51100 includes integrated sleep-state controls, placing VTT in Hi-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The TPS51100 is available in the thermally efficient 10-pin MSOP PowerPAD™ package and is specified from –40°C to 85°C.

下载 观看带字幕的视频 视频

技术文档

star =有关此产品的 TI 精选热门文档
未找到结果。请清除搜索并重试。
查看全部 8
类型 标题 下载最新的英语版本 日期
* 数据表 TPS51100 3-A Sink / Source DDR Termination Regulator 数据表 (Rev. E) PDF | HTML 2014年 12月 17日
应用手册 LDO 噪声揭秘 (Rev. B) PDF | HTML 英语版 (Rev.B) PDF | HTML 2020年 9月 16日
应用手册 DDR VTT Power Solutions: A Competitive Analysis (Rev. A) 2020年 7月 9日
选择指南 电源管理指南 2018 (Rev. K) 2018年 7月 31日
选择指南 电源管理指南 2018 (Rev. R) 2018年 6月 25日
应用手册 LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017年 8月 9日
应用手册 简化的 LDO PSRR 测量 最新英语版本 (Rev.A) PDF | HTML 2010年 7月 28日
用户指南 Using the TPS51100 2004年 7月 13日

设计和开发

如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。

评估板

TPS51116EVM-001 — TPS51116 存储器电源解决方案,同步降压控制器评估模块

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

用户指南: PDF
TI.com 上无现货
仿真模型

TPS51100 PSpice Model

SLVC176.ZIP (473 KB) - PSpice Model
仿真模型

TPS51100 TINA-TI Average Reference Design

SLVC203.ZIP (217 KB) - TINA-TI Reference Design
仿真模型

TPS51100 TINA-TI Average Sink Reference Design (Rev. A)

SLVC177A.ZIP (217 KB) - TINA-TI Reference Design
仿真模型

TPS51100 TINA-TI Average Spice Model

SLVC204.ZIP (7 KB) - TINA-TI Spice Model
仿真模型

TPS51100 TINA-TI Transient Reference Design

SLVC206.ZIP (216 KB) - TINA-TI Reference Design
仿真模型

TPS51100 TINA-TI Transient Spice Model

SLVC205.ZIP (7 KB) - TINA-TI Spice Model
封装 引脚 下载
HVSSOP (DGQ) 10 查看选项

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持和培训

视频