产品详细信息

Number of channels (#) 2 Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Technology Family AHCT Input type TTL-Compatible CMOS Output type Push-Pull ICC (uA) 40 IOL (Max) (mA) 8 IOH (Max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable
Number of channels (#) 2 Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Technology Family AHCT Input type TTL-Compatible CMOS Output type Push-Pull ICC (uA) 40 IOL (Max) (mA) 8 IOH (Max) (mA) -8 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Retriggerable
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SSOP (DB) 16 33 mm² 5.3 x 6.2 TSSOP (PW) 16 22 mm² 4.4 x 5 TVSOP (DGV) 16 23 mm² 3.6 x 6.4
  • Inputs Are TTL-Voltage Compatible
  • Schmitt-Trigger Circuitry On A\, B, and CLR\ Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

  • Inputs Are TTL-Voltage Compatible
  • Schmitt-Trigger Circuitry On A\, B, and CLR\ Inputs for Slow Input Transition Rates
  • Edge Triggered From Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses
  • Overriding Clear Terminates Output Pulse
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A\) or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. CLR\ input can be used to override A\ or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’AHCT123A is shown in Figure 10. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 6.

During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

For additional application information on multivibrators, see the application report, Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.

The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR\ low.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.

Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A\) or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. CLR\ input can be used to override A\ or B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.

The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the ’AHCT123A is shown in Figure 10. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 6.

During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.

For additional application information on multivibrators, see the application report, Designing With the SN74AHC123A and SN74AHCT123A, literature number SCLA014.

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类型 项目标题 下载最新的英语版本 日期
* 数据表 SN54AHCT123A, SN74AHCT123A 数据表 (Rev. G) 02 Apr 2003
应用手册 Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
应用手册 使用 SN74LVC1G123 单稳多谐振荡器进行设计 (Rev. A) PDF | HTML 下载英文版本 (Rev.A) PDF | HTML 20 Jul 2021
选择指南 Little Logic Guide 2014 (Rev. G) 06 Jul 2018
选择指南 Logic Guide (Rev. AB) 12 Jun 2017
应用手册 How to Select Little Logic (Rev. A) 26 Jul 2016
应用手册 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
选择指南 逻辑器件指南 2014 (Rev. AA) 下载最新的英文版本 (Rev.AB) 17 Nov 2014
选择指南 小尺寸逻辑器件指南 (Rev. E) 下载最新的英文版本 (Rev.G) 16 Jul 2012
用户指南 LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
应用手册 选择正确的电平转换解决方案 (Rev. A) 下载英文版本 (Rev.A) 23 Mar 2006
更多文献资料 Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
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更多文献资料 Logic Cross-Reference (Rev. A) 07 Oct 2003
应用手册 Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dec 2002
应用手册 Texas Instruments Little Logic Application Report 01 Nov 2002
应用手册 TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
设计指南 AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
应用手册 Designing With the SN74AHC123A and SN74AHCT123A 01 Oct 1999
更多文献资料 Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
应用手册 Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
应用手册 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
应用手册 CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
应用手册 Live Insertion 01 Oct 1996

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封装 引脚数 下载
PDIP (N) 16 了解详情
SOIC (D) 16 了解详情
SSOP (DB) 16 了解详情
TSSOP (PW) 16 了解详情
TVSOP (DGV) 16 了解详情

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