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参数

Arm CPU 4 Arm Cortex-A53 Arm MHz (Max.) 1100, 1000, 800 Co-processor(s) Arm Cortex-R5F PRU-ICSS Ethernet MAC 10/100/1000, 6-Port 10/100/1000 PRU EMAC PCIe 2 PCIe Gen3 Serial I/O CAN-FD, I2C, SPI, UART, USB DRAM DDR3L-1600, DDR4-1600, LPDDR4-1333 McASP 3 USB 1 USB2.0, 1 USB3.0 EMIF 1x 39-bit with ECC Storage interface 1x SDIO 4b, 1x SDIO 8b, 1x UHSI 4b, 1x eMMC 8b Operating temperature range (C) -40 to 125 Rating Automotive open-in-new 查找其它 DRAx 网关和车辆计算 SoCs

特性

  • Processor cores:
  • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32KB L1 DCache
  • Dual-core Arm® Cortex®-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core
  • Ethernet subsystem:
  • Three industrial subsystem with Ethernet support:
    • Up to two 10/100/1000 Ethernet ports per subsystem
    • Supports two 10/100/1000 SGMII ports (1)
    • Compatibility with 10/100Mb
  • Memory subsystem:
  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR3L/DDR4 memory types up to DDR-1600
    • Supports LPDDR4 memory type up to DDR-1333
    • 32-bit data bus and 7-bit SECDED bus
    • 32GB of total addressable space
  • General-Purpose Memory Controller (GPMC)
  • SafeTI™ semiconductor component:
  • Designed for functional safety applications
  • Developed according to the requirements of ISO 26262
  • Achieves systematic integrity of ASIL-D
  • For the MCU safety island, sufficient diagnostics are included to achieve random fault integrity requirements of ASIL-B
  • For the rest of the SoC, sufficient diagnostics are included to achieve random fault integrity requirements of ASIL-B
  • In addition, sufficient architectural support is in place to achieve execution of ASIL-D applications given a proper safety concept (for example reciprocal comparison by software)
  • Functional safety manual available
  • Safety-related certification
    • Component level functional safety certification by TÜV SÜD [certification in progress]
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm® Cortex®-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC
  • Security:
  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm® TrustZone® based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security
  • SoC services:
  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)
  • Multimedia:
  • One Camera Serial Interface-2 (MIPI® CSI-2)
  • High-speed interfaces:
  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express® (PCIe®) revision 3.1 subsystems (1)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and/or end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (1)
    • One enhanced SuperSpeed Gen1 Port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB dual-role device
  • General connectivity:
  • 6× Inter-Integrated Circuit (I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins
  • Control interfaces:
  • 6× Enhanced High Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • Automotive interfaces:
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Audio interfaces:
  • 3× Multichannel Audio Serial Port (MCASP) modules
  • Media and data storage:
  • 2× MultiMedia Card™/Secure Digital® (MMC™/SD®) interfaces
  • Simplified power management:
  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients
  • Analog/system integration:
  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change
  • System-on-Chip (SoC) architecture:
  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

All trademarks are the property of their respective owners.

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描述

Automobiles are becoming more and more connected - both inside the car, within the various subsystems/domains as well as with the outside world, with connectivity via Bluetooth, LTE, WiFi etc.

Much more information and data are being shared or transferred between the various domains; for example, video from rear and surround view cameras for displayed in the head unit; data from the chassis is sent to the on-board diagnostic unit, etc. As the amount of data that has to be integrated and transported between the various domains in a time sensitive manner has increased, car manufacturers are looking to include a network gateway, based on Ethernet protocols, in cars. Such gateways should be able to handle multiple connectivity protocols such as CAN, CAN-FD, TCP/IP to name a few. TI’s DRA80x family of products enable automotive manufacturers to build scalable and cost optimized network gateway features in cars, thanks to its high level of integration and purpose built peripherals, such as Gigabit Ethernet MACs.

DRA80x Jacinto Automotive Gateway processors are built to meet the intense processing needs of automotive gateway. The DRA80x family of devices combines four or two Arm® Cortex®-A53 cores with an ASIL-C capable dual Arm® Cortex®-R5 MCU subsystem and six Gigabit Ethernet MACs in the MAIN domain and one Gigabit Ethernet MAC in the MCU domain to create an SoC capable of implementing an Automotive Gateway system with plenty of automotive connectivity and functional safety processing.

The four Cortex-A53 cores in the DRA804M are arranged in two dual-core clusters with shared L2 memory to create two processing channels to address additional safety concepts. The two Arm® Cortex®-A53 cores in the DRA802M are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included for on-chip memory and interconnects for reliability. Cryptographic acceleration and secure boot are available on some DRA80x devices, in addition to granular whitelist firewalls managed by a security controller core.

Programmability is provided by the Arm® Cortex®-A53 RISC CPUs with Arm® Neon™ extension, and the dual Arm® Cortex®-R5 MCU subsystem is available for general purpose use. The Ethernet subsystem can be used to provide up to six ports of Ethernets, including TSN and Ethernet/IP, for standard Ethernet connectivity. Additionally, TI provides a complete set of development tools for the Arm® cores including C compilers and a debugging interface for visibility into source code execution. Safety documentation is available for applications needing to meet functional safety standards.

open-in-new 查找其它 DRAx 网关和车辆计算 SoCs
下载

样品供货情况

ACD 封装目前处于预发行状态。可提供试生产样品 (X6580AACD)。立即申请

技术文档

= 特色
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类型 标题 下载最新的英文版本 发布
* 数据表 DRA80xM Jacinto™ Infotainment Applications Processor Silicon Revision 2.0 数据表 2019年 11月 11日
* 勘误表 AM65x/DRA80xM Processors Silicon Revision 1.0 2019年 12月 23日
应用手册 AM65x/DRA80xM EMIF Tools 2020年 3月 4日
白皮书 Evolving automotive gateways for next-generation vehicles. 2020年 3月 1日
白皮书 Evolving automotive gateways for next-generation vehicles. 2020年 2月 26日
用户指南 AM65x/DRA80xM Processors Technical Reference Manual 2019年 12月 18日
白皮书 研发适用于下一代汽车的汽车网关 (Rev. A) 下载英文版本 (Rev.A) 2019年 12月 10日
应用手册 AM65x/DRA80xM DDR Board Design and Layout Guidelines 2019年 3月 7日
应用手册 Hardware Design Guide for AM65x/DRA80xM Devices 2018年 10月 11日
应用手册 AM65x Schematic Checklist 2018年 10月 4日
用户指南 AM654x BGA Escape Routing Stackup 2018年 8月 29日
技术文章 Smart sensors are going to change how you drive (because eventually, you won’t) 2018年 4月 25日
技术文章 AI in Automotive: Practical deep learning 2018年 2月 8日
技术文章 How to maintain automotive front camera thermal performance on a hot summer day 2018年 2月 2日
技术文章 Development platforms pave the way to production systems for ADAS 2018年 1月 19日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

硬件开发

评估板 下载
document-generic 用户指南
说明
DRA80xM 评估模块 (EVM) 是一款用于为汽车网关和域控制器应用评估 Jacinto™ DRA80xM 处理器高速网络功能的开发平台。DRA80xM 器件具有 Arm® Cortex-A53 主处理单元 (MPU) 和辅助的 Arm® Cortex-R5F MPU,可执行时间敏感型任务。此 EVM 还集成了众多外设,包括千兆以太网、PCIe 第 3.1 代和 CAN-FD。
特性
  • 具备 ECC 保护的 4GB DDR4
  • 板载 16GB eMMC
  • 板载 512Mb OSPI 闪存
  • 千兆以太网、PCIe 第 3.1 代、CAN-FD 和 USB 2.0 接口

软件开发

软件开发套件 (SDK) 下载
适用于 DRA8x Jacinto™ 处理器的处理器软件开发套件
PROCESSOR-SDK-DRA8X — Processor SDK Linux Automotive 是用于 TI Jacinto™ DRAx 系列信息娱乐系统/网关 SoC (...)
特性
  • 开放的 Linux 支持
  • Linux 内核和引导加载程序
  • 文件系统
  • 示例应用,包括:
    • ARM 基准测试:Dhrystone、Linpack、Whetstone
    • 加密:AES、3DES、MD5、SHA
    • 可编程实时单元 (PRU)
    • 用于进行核间通信的 IPC
    • 用于实时内核的 TI-RTOS
  • 主机工具,包括闪存工具和引脚复用实用程序
  • 用于 Linux 开发的 Code Composer Studio™ IDE
  • 文档

设计工具和仿真

仿真模型 下载
SPRM718.ZIP (2 KB) - Thermal Model
仿真模型 下载
SPRM724.ZIP (12 KB) - BSDL Model
仿真模型 下载
SPRM737.ZIP (19753 KB) - IBIS Model
计算工具 下载
Clock Tree Tool for Sitara™ ARM® Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
document-generic 用户指南
计算工具 下载

CAD/CAE 符号

封装 引脚 下载
FCBGA (ACD) 784 视图选项

订购与质量

支持与培训

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