Altium

Design Rule Verification Report

Date: 8/9/2017
Time: 1:43:44 PM
Elapsed Time: 00:00:05
Filename: C:\Users\a0227001\Desktop\TIDA01478\TIDA-01478\TIDA-01478_PCB.PcbDoc
Warnings: 0
Rule Violations: 31

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Clearance Constraint (Gap=25mil) (InPolygon),(All) 0
Clearance Constraint (Gap=0mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=20mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Minimum Annular Ring (Minimum=5.905mil) (IsVia and InAnyComponent) 0
Acute Angle Constraint (Minimum=45.000) (All) 1
Hole Size Constraint (Min=7.874mil) (Max=251mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 5
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Silk To Solder Mask (Clearance=4mil) (All),(All) 17
Silk To Solder Mask (Clearance=5mil) ((IsPad or IsFill or IsRegion) and InAnycomponent),(All) 7
Silk to Silk (Clearance=4mil) (All),(All) 1
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Net Antennae (Tolerance=0mil) (All) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and IsPoly) 0
Board Clearance Constraint (Gap=0mil) (OnCopper and InComponentClass('Mounting Holes')) 0
Component Clearance Constraint ( Horizontal Gap = 40mil, Vertical Gap = 30mil ) (IsThruComponent),(IsSMTComponent) 0
Component Clearance Constraint ( Horizontal Gap = 12mil, Vertical Gap = 10mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 0
Component Clearance Constraint ( Horizontal Gap = 20mil, Vertical Gap = 10mil ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 30mil ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 250mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 31

Acute Angle Constraint (Minimum=45.000) (All)
Acute Angle Constraint: (45.000 < 45.000) Between Track (1080mil,730mil)(1105.622mil,704.378mil) on Top Layer And Pad R5-2(1117mil,701.378mil) on Top Layer (Angle = 45.000)

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Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (1.134mil < 3.937mil) Between Via (966mil,858mil) from Top Layer to Bottom Layer And Pad U1-3(992.882mil,857mil) on Top Layer [Top Solder] Mask Sliver [1.134mil]
Minimum Solder Mask Sliver Constraint: (3.81mil < 3.937mil) Between Via (883mil,907mil) from Top Layer to Bottom Layer And Pad C1-1(909mil,870.496mil) on Top Layer [Top Solder] Mask Sliver [3.81mil]
Minimum Solder Mask Sliver Constraint: (3.693mil < 3.937mil) Between Via (1816.598mil,911.504mil) from Top Layer to Bottom Layer And Pad D2-2(1755.598mil,912.244mil) on Top Layer [Top Solder] Mask Sliver [3.693mil]
Minimum Solder Mask Sliver Constraint: (3.252mil < 3.937mil) Between Via (1610mil,941mil) from Top Layer to Bottom Layer And Pad R6-1(1617.622mil,974mil) on Top Layer [Top Solder] Mask Sliver [3.252mil]
Minimum Solder Mask Sliver Constraint: (3.093mil < 3.937mil) Between Via (1442.598mil,833.504mil) from Top Layer to Bottom Layer And Via (1460.782mil,813.504mil) from Top Layer to Bottom Layer [Top Solder] Mask Sliver [3.093mil] / [Bottom Solder] Mask Sliver [3.093mil]

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Silk To Solder Mask (Clearance=4mil) (All),(All)
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1200.5mil,738mil)(1200.5mil,761mil) on Top Overlay And Via (1197mil,723mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1159.5mil,738mil)(1200.5mil,738mil) on Top Overlay And Via (1197mil,723mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.726mil < 4mil) Between Track (952.5mil,749mil)(952.5mil,772mil) on Top Overlay And Via (938.378mil,736mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.726mil]
Silk To Solder Mask Clearance Constraint: (3.446mil < 4mil) Between Track (1472mil,937.5mil)(1495mil,937.5mil) on Top Overlay And Via (1513mil,950mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.446mil]
Silk To Solder Mask Clearance Constraint: (1.049mil < 4mil) Between Track (1370.734mil,825.982mil)(1425.2mil,825.982mil) on Top Overlay And Via (1398mil,850mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [1.049mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (881.8mil,873mil)(881.8mil,898.982mil) on Top Overlay And Via (883mil,907mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (0.531mil < 4mil) Between Track (867mil,866mil)(867mil,926mil) on Top Overlay And Via (883mil,907mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0.531mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (881.8mil,898.982mil)(936.266mil,898.982mil) on Top Overlay And Via (883mil,907mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1619mil,953.5mil)(1642mil,953.5mil) on Top Overlay And Via (1610mil,941mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Text "C7" (1294mil,892mil) on Top Overlay And Via (1281mil,899mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1226.976mil,715.913mil)(1246.858mil,715.913mil) on Top Overlay And Via (1225mil,701mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (2.13mil < 4mil) Between Track (1222mil,898.5mil)(1222mil,939.5mil) on Top Overlay And Via (1242.598mil,904.364mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [2.13mil]
Silk To Solder Mask Clearance Constraint: (2.948mil < 4mil) Between Track (1199mil,898.5mil)(1222mil,898.5mil) on Top Overlay And Via (1242.598mil,904.364mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [2.948mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1829.5mil,821mil)(1829.5mil,996mil) on Top Overlay And Via (1816.598mil,911.504mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 4mil) Between Track (1814.099mil,702.504mil)(1814.099mil,943.504mil) on Top Overlay And Via (1816.598mil,911.504mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (3.486mil < 4mil) Between Track (1425.2mil,800mil)(1425.2mil,825.982mil) on Top Overlay And Via (1442.598mil,833.504mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.486mil]
Silk To Solder Mask Clearance Constraint: (3.486mil < 4mil) Between Track (1370.734mil,825.982mil)(1425.2mil,825.982mil) on Top Overlay And Via (1442.598mil,833.504mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [3.486mil]

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Silk To Solder Mask (Clearance=5mil) ((IsPad or IsFill or IsRegion) and InAnycomponent),(All)
Silk To Solder Mask Clearance Constraint: (4.484mil < 5mil) Between Track (757mil,856mil)(797mil,856mil) on Top Overlay And Pad L1-2(812mil,884.457mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.484mil]
Silk To Solder Mask Clearance Constraint: (4.484mil < 5mil) Between Track (837mil,822mil)(837mil,856mil) on Top Overlay And Pad L1-2(812mil,884.457mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.484mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Track (757mil,866mil)(812mil,866mil) on Top Overlay And Pad L1-2(812mil,884.457mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (4.484mil < 5mil) Between Track (797mil,856mil)(837mil,856mil) on Top Overlay And Pad L1-2(812mil,884.457mil) on Top Layer [Top Overlay] to [Top Solder] clearance [4.484mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Track (812mil,866mil)(867mil,866mil) on Top Overlay And Pad L1-2(812mil,884.457mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Area Fill (1862mil,772mil) (1882mil,864mil) on Top Overlay And Via (1872mil,803mil) from Top Layer to Bottom Layer [Top Overlay] to [Top Solder] clearance [0mil]
Silk To Solder Mask Clearance Constraint: (Collision < 5mil) Between Area Fill (1862mil,772mil) (1882mil,864mil) on Top Overlay And Track (1872mil,803mil)(1872mil,844.532mil) on Top Layer [Top Overlay] to [Top Solder] clearance [0mil]

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Silk to Silk (Clearance=4mil) (All),(All)
Silk To Silk Clearance Constraint: (2mil < 4mil) Between Text "D3" (1923.5mil,983.5mil) on Top Overlay And Track (1914.5mil,821mil)(1914.5mil,996mil) on Top Overlay Silk Text to Silk Clearance [2mil]

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