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Design Rule Verification Report

Date : 3/26/2014
Time : 7:22:56 PM
Elapsed Time : 00:00:06
Filename : D:\Temperature Sensor Module for PLC\Completed\Design files\TIDA-00018.PcbDoc
Warnings : 0
Rule Violations : 8

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=20mil) (IsKeepOut),(InPolygon) 0
Clearance Constraint (Gap=7.7mil) (InPadClass('PAD Class')),(InPadClass('PAD Class')) 0
Clearance Constraint (Gap=8mil) (IsVia),(IsSMTPin) 8
Clearance Constraint (Gap=10mil) (IsVia),(IsVia) 0
Clearance Constraint (Gap=12mil) (IsVia),(InPolygon) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('EVM')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('I2C1')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('CJT1')) 0
Width Constraint (Min=10mil) (Max=40mil) (Preferred=12mil) (All) 0
Clearance Constraint (Gap=40mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=10mil) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=25mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and Not IsKeepout),(IsKeepOut) 0
Clearance Constraint (Gap=20mil) (InPolygon),(All) 0
Clearance Constraint (Gap=7.5mil) (All),(All) 0
Width Constraint (Min=10mil) (Max=40mil) (Preferred=12mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=10mil) (Conductor Width=15mil) (Air Gap=12mil) (Entries=4) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=16mil) (MinWidth=24mil) (MaxWidth=40mil) (PreferedWidth=30mil) (IsVia and InAnyComponent) 0
Routing Via (MinHoleWidth=12mil) (MaxHoleWidth=20mil) (PreferredHoleWidth=16mil) (MinWidth=24mil) (MaxWidth=40mil) (PreferedWidth=32mil) (All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Minimum Annular Ring (Minimum=6mil) (All) 0
Hole Size Constraint (Min=8mil) (Max=251mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('RTD')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('RTD_1')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('RTDREF')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('TCP')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('TC_1')) 0
Width Constraint (Min=12mil) (Max=40mil) (Preferred=12mil) (InDifferentialPair('CJT')) 0
Clearance Constraint (Gap=12mil) (IsSMTPin),(InPolygon) 0
Total 8


Clearance Constraint (Gap=8mil) (IsVia),(IsSMTPin)
Via (638.622mil,1761.378mil) Top Layer to Bottom Layer Pad U1-9(615mil,1785mil) Top Layer
Via (638.622mil,1808.622mil) Top Layer to Bottom Layer Pad U1-9(615mil,1785mil) Top Layer
Via (591.378mil,1761.378mil) Top Layer to Bottom Layer Pad U1-9(615mil,1785mil) Top Layer
Via (591.378mil,1808.622mil) Top Layer to Bottom Layer Pad U1-9(615mil,1785mil) Top Layer
Via (2057.284mil,1776.378mil) Top Layer to Bottom Layer Pad U2-9(2075mil,1800mil) Top Layer
Via (2057.284mil,1823.622mil) Top Layer to Bottom Layer Pad U2-9(2075mil,1800mil) Top Layer
Via (2092.716mil,1776.378mil) Top Layer to Bottom Layer Pad U2-9(2075mil,1800mil) Top Layer
Via (2092.716mil,1823.622mil) Top Layer to Bottom Layer Pad U2-9(2075mil,1800mil) Top Layer
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