adc08d1520 Project Status (05/21/2012 - 15:34:36)
Project File: adc08d1520.xise Parser Errors: No Errors
Module Name: adc08d1520 Implementation State: Programming File Generated
Target Device: xc4vlx25-11ff668
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
214 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
X 2 Failing Constraints
Environment: System Settings
  • Final Timing Score:
36574  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 1,511 21,504 7%  
Number of 4 input LUTs 1,085 21,504 5%  
Number of occupied Slices 1,233 10,752 11%  
    Number of Slices containing only related logic 1,233 1,233 100%  
    Number of Slices containing unrelated logic 0 1,233 0%  
Total Number of 4 input LUTs 1,232 21,504 5%  
    Number used as logic 1,085      
    Number used as a route-thru 147      
Number of bonded IOBs 305 448 68%  
    IOB Flip Flops 193      
    IOB Dual-Data Rate Flops 48      
    IOB Master Pads 56      
    IOB Slave Pads 56      
Number of BUFG/BUFGCTRLs 7 32 21%  
    Number used as BUFGs 7      
Number of FIFO16/RAMB16s 48 72 66%  
    Number used as RAMB16s 48      
Number of DCM_ADVs 5 8 62%  
Average Fanout of Non-Clock Nets 2.98      
 
Performance Summary [-]
Final Timing Score: 36574 (Setup: 36574, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: X 2 Failing Constraints    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon May 21 16:15:01 2012091 Warnings (0 new)59 Infos (0 new)
Translation ReportCurrentMon May 21 16:15:13 201209 Warnings (0 new)10 Infos (0 new)
Map ReportCurrentMon May 21 16:15:25 2012067 Warnings (0 new)5 Infos (0 new)
Place and Route ReportCurrentMon May 21 16:16:30 2012025 Warnings (0 new)1 Info (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon May 21 16:16:40 2012003 Infos (0 new)
Bitgen ReportCurrentMon May 21 16:16:59 2012022 Warnings (0 new)1 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentMon May 21 16:17:00 2012

Date Generated: 06/19/2012 - 08:58:56