Protel Design System Design Rule Check
PCB File : C:\Users\a0488740\Downloads\sprr452\Layout\PROC111E2.PcbDoc
Date     : 4/16/2025
Time     : 9:58:54 AM

Processing Rule : Clearance Constraint (Gap=4mil) (WithinRoom('SOC_4mil')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7.874mil) ((OnLayer('Top Layer') or OnLayer('Bottom Layer'))),(InNetClass('ADC0'))
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7.874mil) (InDifferentialPairClass('100E')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7.874mil) (InDifferentialPairClass('100E')),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7.874mil) (All),(InDifferentialPair('XDSET_1_D'))
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=7.874mil) (OnLayer('SIG 1')),(InNetClass('ADC0'))
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=10mil) (InPolygon),(All)
Rule Violations :0

Processing Rule : Clearance Constraint (Gap=1mil) (IsKeepOut),(All)
   Violation between Clearance Constraint: (Collision < 1mil) Between Arc (113.789mil,1771.827mil) on Top Layer And Pad FID3-1(113.789mil,1771.827mil) on Top Layer 
   Violation between Clearance Constraint: (Collision < 1mil) Between Arc (113.789mil,392.065mil) on Top Layer And Pad FID2-1(113.789mil,392.065mil) on Top Layer 
   Violation between Clearance Constraint: (Collision < 1mil) Between Arc (6995.38mil,2165mil) on Top Layer And Pad FID1-1(6995.38mil,2165mil) on Top Layer 
Rule Violations :3

Processing Rule : Clearance Constraint (Gap=7.874mil) (All),(All)
Rule Violations :0

Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
   Violation between Short-Circuit Constraint: Between Pad U1-N3(3610.125mil,1004.842mil) on Top Layer And Track (3594.377mil,989.095mil)(3610.125mil,1004.842mil) on Top Layer Location : [X = 4300.746mil][Y = 2537.463mil]
Rule Violations :1

Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0

Processing Rule : Routing Layers(All)
Rule Violations :0

Processing Rule : Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent)
Rule Violations :0

Processing Rule : Routing Via (MinHoleWidth=8mil) (MaxHoleWidth=8mil) (PreferredHoleWidth=8mil) (MinWidth=18mil) (MaxWidth=18mil) (PreferedWidth=18mil) (All)
Rule Violations :0

Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=5mil) (Max=10mil) (Prefered=10mil)  and Width Constraints (Min=4mil) (Max=15mil) (Prefered=15mil) (InDifferentialPair('XDSET_1_D'))
Rule Violations :0

Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=6.8mil) (Max=10mil) (Prefered=10mil)  and Width Constraints (Min=4.1mil) (Max=15mil) (Prefered=15mil) (InDifferentialPair('CANA'))
Rule Violations :0

Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=7.7mil) (Max=100mil) (Prefered=10mil)  and Width Constraints (Min=3.5mil) (Max=15mil) (Prefered=15mil) (InDifferentialPairClass('100E'))
Rule Violations :0

Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0

Processing Rule : Minimum Annular Ring (Minimum=5mil) (All)
   Violation between Minimum Annular Ring: (No Ring) Pad J5-3(936.456mil,69.685mil) on Multi-Layer (Annular Ring missing on Top Layer)
   Violation between Minimum Annular Ring: (No Ring) Pad J5-4(1300.236mil,69.685mil) on Multi-Layer (Annular Ring missing on Top Layer)
Rule Violations :2

Processing Rule : Minimum Annular Ring (Minimum=5.906mil) (IsVia and InAnyComponent)
Rule Violations :0

Processing Rule : Hole Size Constraint (Min=7.874mil) (Max=251mil) (All)
Rule Violations :0

Processing Rule : Pads and Vias to follow the Drill pairs settings
Rule Violations :0

Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0

Processing Rule : Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo'))
Rule Violations :0

Processing Rule : Silk To Solder Mask (Clearance=3mil) (All),(All)
   Violation between Silk To Solder Mask Clearance Constraint: (1.772mil < 3mil) Between Pad U34-1(678.78mil,2146.969mil) on Top Layer And Track (689.606mil,2135.158mil)(689.606mil,2154.843mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.772mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.772mil < 3mil) Between Pad U34-3(651.221mil,2146.969mil) on Top Layer And Track (640.394mil,2146.969mil)(640.394mil,2154.843mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.772mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.772mil < 3mil) Between Pad U34-4(651.221mil,2115.473mil) on Top Layer And Track (640.394mil,2107.599mil)(640.394mil,2115.473mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.772mil]
   Violation between Silk To Solder Mask Clearance Constraint: (1.772mil < 3mil) Between Pad U34-6(678.78mil,2115.473mil) on Top Layer And Track (689.606mil,2107.599mil)(689.606mil,2115.473mil) on Top Overlay [Top Overlay] to [Top Solder] clearance [1.772mil]
Rule Violations :4

Processing Rule : Silk To Solder Mask (Clearance=3.541mil) ((IsPad or IsFill or IsRegion) and Component),(All)
Rule Violations :0

Processing Rule : Silk to Silk (Clearance=3.937mil) (All),(All)
   Violation between Silk To Silk Clearance Constraint: (1.54mil < 3.937mil) Between Area Fill (2659.449mil,2111.877mil) (2679.134mil,2174.869mil) on Top Overlay And Text "D7" (2642.5mil,2099mil) on Top Overlay Silk Text to Silk Clearance [1.54mil]
Rule Violations :1

Processing Rule : Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small')))
Rule Violations :0

Processing Rule : Net Antennae (Tolerance=0mil) (All)
   Violation between Net Antennae: Track (3541.117mil,924.878mil)(3544.783mil,924.878mil) on Top Layer 
Rule Violations :1

Processing Rule : Board Clearance Constraint (Gap=0mil) (OnCopper and InComponentClass('Mounting Holes'))
Rule Violations :0

Processing Rule : Board Clearance Constraint (Gap=0mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and not InPoly)
   Violation between Board Outline Clearance(Outline Edge): (15.748mil < 40mil) Between Board Edge And Pad J34-10(57.086mil,888.564mil) on Multi-Layer 
   Violation between Board Outline Clearance(Outline Edge): (15.748mil < 40mil) Between Board Edge And Pad J34-7(57.086mil,1199.588mil) on Multi-Layer 
   Violation between Board Outline Clearance(Outline Edge): (19.685mil < 40mil) Between Board Edge And Pad J34-8(57.086mil,1080.986mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (19.685mil < 40mil) Between Board Edge And Pad J34-9(57.086mil,1007.167mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.347mil < 40mil) Between Board Edge And Pad J5-3(936.456mil,69.685mil) on Multi-Layer 
   Violation between Board Outline Clearance(Outline Edge): (18.504mil < 40mil) Between Board Edge And Pad J5-3(936.456mil,89.37mil) on Bottom Layer 
   Violation between Board Outline Clearance(Outline Edge): (18.504mil < 40mil) Between Board Edge And Pad J5-3(936.456mil,89.37mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.347mil < 40mil) Between Board Edge And Pad J5-4(1300.236mil,69.685mil) on Multi-Layer 
   Violation between Board Outline Clearance(Outline Edge): (18.504mil < 40mil) Between Board Edge And Pad J5-4(1300.236mil,89.37mil) on Bottom Layer 
   Violation between Board Outline Clearance(Outline Edge): (18.504mil < 40mil) Between Board Edge And Pad J5-4(1300.236mil,89.37mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.032mil < 40mil) Between Board Edge And Pad SW2-2(367.323mil,2252.284mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.032mil < 40mil) Between Board Edge And Pad SW2-4(587.795mil,2252.284mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.032mil < 40mil) Between Board Edge And Pad SW3-2(839.764mil,2252.284mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.032mil < 40mil) Between Board Edge And Pad SW3-4(1060.236mil,2252.284mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.032mil < 40mil) Between Board Edge And Pad SW4-2(1264.764mil,2252.283mil) on Top Layer 
   Violation between Board Outline Clearance(Outline Edge): (28.032mil < 40mil) Between Board Edge And Pad SW4-4(1485.236mil,2252.283mil) on Top Layer 
Rule Violations :16

Processing Rule : Board Clearance Constraint (Gap=0mil) (OnCopper and IsPoly)
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('ETH1_TX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('ICSSM_MII0_RX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('ICSSM_MII0_TX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=25mil) (InxSignalClass('MMC0'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=2mil) (All)
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('ETH1_RX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('AM263_RGMII1_RX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('PRO_PROU_GPIO(0-6)'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('PRO_PROU_GPIO(11-16)'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('ICSSM_MII1_TX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('ICSSM_MII1_RX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=7.5mil) (InxSignalClass('AM263_RGMII1_TX'))
Rule Violations :0

Processing Rule : Matched Lengths(Tolerance=25mil) (InxSignalClass('QSPI_FLASH'))
Rule Violations :0

Processing Rule : Room SOC_4mil (Bounding Region = (4207.637mil, 2349.866mil, 4806.063mil, 2948.292mil) (False)
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 10mil, Vertical Gap = 10mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 100mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 20mil, Vertical Gap = 30mil ) (IsThruComponent),(IsThruComponent) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 15mil, Vertical Gap = 15mil ) (All),(All) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 
Rule Violations :0

Processing Rule : Component Clearance Constraint ( Horizontal Gap = 30mil, Vertical Gap = 30mil ) (IsThruComponent),(IsSMTComponent) 
Rule Violations :0

Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0


Violations Detected : 28
Waived Violations : 0
Time Elapsed        : 00:00:27