.ALIASES
C_C2            C2(1=VDD 2=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787577@ANALOG.C.Normal(chips)
C_C1            C1(1=HB 2=HS ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787826@ANALOG.C.Normal(chips)
X_S3    S3(1=LO 2=0 3=HS 4=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787600@ANALOG.S.Normal(chips)
V_V10           V10(+=N16787627 -=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787864@SOURCE.VDC.Normal(chips)
V_V2            V2(+=PWM_LI -=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16779907@SOURCE.VPULSE.Normal(chips)
X_U4            U4(1=BST 2=HB ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787145@DIODES.D_D1.Normal(chips)
C_C5            C5(1=0 2=N16787627 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787630@ANALOG.C.Normal(chips)
L_L1            L1(1=HS 2=VOUT ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787638@ANALOG.L.Normal(chips)
V_V11           V11(+=VDD -=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16779941@SOURCE.VPWL.Normal(chips)
C_C3            C3(1=0 2=VOUT ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787656@ANALOG.C.Normal(chips)
X_U5            U5(HB=HB HO=HO PWM_LI=PWM_LI HS_0=HS HS_1=HS HS_2=HS HS_3=HS HS_DAP=0 LS_DAP=0 VIN=VDD LO=LO DHL=N16779560
+DLH=N16779555 VCC=VDD VSS_0=0 VSS_1=0 HI_EN=EN_HI NC_0=0 NC_1=0 NC_2=0 BST=BST ) CN
+@LMG1210.Test_TOP_PWM(sch_1):INS16780660@LMG1210RVR_TRANS.LMG1210RVR_TRANS.Normal(chips)
R_R1            R1(1=0 2=VOUT ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787670@ANALOG.R.Normal(chips)
X_S4    S4(1=HO 2=HS 3=N16787627 4=HS ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787691@ANALOG.S.Normal(chips)
R_R5            R5(1=0 2=N16779555 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16779523@ANALOG.R.Normal(chips)
X_U3            U3(1=0 2=HS ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787717@DIODES.D_D1.Normal(chips)
L_L2            L2(1=N16788727 2=VOUT_IDEAL ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16788684@ANALOG.L.Normal(chips)
R_R6            R6(1=0 2=N16779560 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16779537@ANALOG.R.Normal(chips)
C_C4            C4(1=0 2=VOUT_IDEAL ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16788707@ANALOG.C.Normal(chips)
R_R2            R2(1=0 2=VOUT_IDEAL ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16788715@ANALOG.R.Normal(chips)
C_C6            C6(1=0 2=N16787627 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787760@ANALOG.C.Normal(chips)
X_U2            U2(1=HS 2=N16787627 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787768@DIODES.D_D1.Normal(chips)
V_V4            V4(+=N16788727 -=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16788748@SOURCE.VPULSE.Normal(chips)
V_V3            V3(+=EN_HI -=0 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16780083@SOURCE.VPULSE.Normal(chips)
C_C7            C7(1=0 2=N16787627 ) CN @LMG1210.Test_TOP_PWM(sch_1):INS16787810@ANALOG.C.Normal(chips)
_    _(BST=BST)
_    _(VDD=VDD)
_    _(EN_HI=EN_HI)
_    _(LO=LO)
_    _(HO=HO)
_    _(HS=HS)
_    _(PWM_LI=PWM_LI)
_    _(HB=HB)
_    _(vout=VOUT)
_    _(vout_ideal=VOUT_IDEAL)
.ENDALIASES
