This subsystem demonstrates how to simultaneously sample signals across 2 ADC instances by utilizing the event fabric of the MSPM0. This process reduces time skew and keeps the signals in phase, simplifying calculations for applications such as E-metering, motor control, or medical signal processing.

Figure 1-1 Simultaneous Sampling Functional Block Diagram

This application requires two integrated ADCs, a DMA module with at least two channels, and a TIM module.

1. Determine the configuration for the ADCs including reference source, reference value, resolution, and sampling rate based on the given analog input and design requirements.
2. Determine the period of the timer that triggers the ADCs based on design requirements.
3. Generate two array buffers with sizes matching those of the DMA transfer size to store all of the ADC conversion results.
4. In SysConfig, configure the timer as an event publisher to a 1:2 channel and have each ADC configured as a subscriber to the same channel.
5. Write Application Code to start the timer and process the simultaneously sampled data.

1. Maximum Sampling Speed: The sampling speed of the ADC is based on input signal frequency, analog front end, filters, or any other design parameters that affect sampling.
2. ADC Reference: Choose the reference to align with the expected maximum input to utilize the full scale range of the ADC.
3. Clock Settings: The clock source determines the total time for the conversion. The clock divider in tandem with the SCOMP setting determines the total sampling time. SysConfig sets the appropriate SCOMP depending on the sampling time setting.
4. Timer Period: The timer period is based on how frequently the system needs to sample the input signals. Different combinations of Timer Clock Divider and Timer Clock Prescaler in SysConfig can provide the desired resolution.